參數(shù)資料
型號(hào)： DS21448LN+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 19/60頁(yè)
文件大?。?/td> 0K
描述： IC LIU QUAD E1/T1/J1 128-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 72
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： T1/E1/J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x20）
包裝： 管件
DS21448 3.3V T1/E1/J1 Quad Line Interface
26 of 60
RIR1 (08H): Receive Information Register 1
(MSB)
(LSB)
ZD
16ZD
HBD
RCLC
RUA1C
JALT
—
NAME
POSITION
FUNCTION
ZD
(Latched)
RIR1.7
Zero Detect. This bit is set when a string of at least four (ETS = 0) or eight (ETS = 1)
consecutive 0s (regardless of the length of the string) have been received. This bit is cleared
when read.
16ZD
(latched)
RIR1.6
16 Zero Detect. This is set when at least 16 consecutive 0s (regardless of the length of the
string) have been received. This bit is cleared when read.
HBD
(Latched)
RIR1.5
HDB3/B8ZS Word Detect. This is set when an HDB3 (ETS = 0) or B8ZS (ETS = 1) codeword
is detected independently of the receive HDB3/B8ZS mode (CCR4.6) being enabled. This bit
is cleared when read. It is useful for automatically setting the line coding.
RCLC
(Latched)
RIR1.4
RCL Clear. Set when the RCL alarm has met the clear criteria defined in Table 5-A. This bit
is cleared when read.
RUA1C
(Latched)
RIR1.3
Receive Unframed All-Ones Clear. This bit is set when the unframed all-ones signal is no
longer detected. This bit is cleared when read (Table 5-A).
JALT
(Latched)
RIR1.2
Jitter Attenuator Limit Trip. This bit is set when the jitter attenuator FIFO reaches within 4 bits
of its useful limit. This bit is cleared when read and is useful for debugging jitter attenuation
operation.
N/A
RIR1.1
Not Assigned. Could be any value when read.
N/A
RIR1.0
Not Assigned. Could be any value when read.
RIR2 (09H): Receive Information Register 2
(MSB)
(LSB)
RL3
RL2
RL1
RL0
—
ARLB
SEC
NAME
POSITION
FUNCTION
RL3
(Real Time)
RIR2.7
Receive Level Bit 3 (Table 5-B)
RL2
(Real Time)
RIR2.6
Receive Level Bit 2
RL1
(Real Time)
RIR2.5
Receive Level Bit 1 (Table 5-B)
RL0
(Real Time)
RIR2.4
Receive Level Bit 0
N/A
RIR2.3
Not Assigned. Could be any value when read.
N/A
RIR2.2
Not Assigned. Could be any value when read.
ARLB
(Real Time)
RIR2.1
Automatic Remote Loopback Detected. This bit is set to 1 when the automatic remote
loopback circuitry has detected the presence of a loop-up code for 5 seconds. It remains set
until the automatic RLB circuitry has detected the loop-down code for 5 seconds. See
Section 11 for more details. This bit is forced low when the automatic RLB circuitry is
disabled (CCR6.5 = 0).
SEC
(Latched)
RIR2.0
One-Second Timer. This bit is set to 1 on one-second boundaries as timed by the device,
based on the RCLK. It is cleared when read.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21448LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21448-LW 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21448N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V E1/T1/J1 Quad Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2145 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC
DS21455 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1-T1-J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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