- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4573 > DS1865T+T&R (Maxim Integrated Products)IC PON CONTROL TRI 28-TQFN PDF資料下載
參數(shù)資料
| 型號(hào)： | DS1865T+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 7/67頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PON CONTROL TRI 28-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
| 類型： | * |
| 應(yīng)用： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)
DS1865
PON Triplexer Control and
Monitoring Circuit
____________________________________________________________________
15
inadequate VCC exists to operate the laser driver. Once
adequate VCC is present to clear the VCC low alarm, the
outputs are enabled following the same sequence as the
power-up sequence.
As previously mentioned, the FETG is an output used to
disable the laser current through a series nMOSFET or
pMOSFET. This requires that the FETG output can sink
or source current. Because the DS1865 does not know
if it should sink or source current before VCC exceeds
VPOA, which triggers the EE recall, this output will
be high impedance when VCC is below VPOA (see the
Low-Voltage Operation section for details and
diagram). The application circuit must use a pullup or
pulldown resistor on this pin that pulls FETG to the
alarm/shutdown state (high for a pMOS, low for a
nMOS). Once VCC is above VPOA, the DS1865 pulls the
FETG output to the state determined by the FETG DIR
bit (Table 02h, Register 89h). FETG DIR is 0 if an nMOS
is used and 1 if a pMOS is used.
Determining Alarm Causes
Using the I2C Interface
To determine the cause of the TX-F or FETG alarm, the
system processor can read the DS1865’s Alarm Trap
Bytes (ATB) through the I2C interface (in Table 01h). The
ATB has a bit for each alarm. Any time an alarm occurs,
regardless of the mask bit’s state, the DS1865 sets the
corresponding bit in the ATB. Active ATB bits remain set
until written to zeros through the I2C interface. On power-
up, the ATB is zeros until alarms dictate otherwise.
Die Identification
The DS1865 has an ID hard coded to its die. Two regis-
ters (Table 02h bytes 86h–87h) are assigned for this
feature. Byte 86h reads 65h to identify the part as the
DS1865, byte 87h reads the die revision.
Low-Voltage Operation
The DS1865 contains two power-on reset (POR) levels.
The lower level is a digital POR (VPOD) and the higher
level is an analog POR (VPOA). At startup, before the
supply voltage rises above VPOA, the outputs are dis-
abled (FETG and BIAS outputs are high impedance,
MOD is low), all SRAM locations are low (including
shadowed EEPROM), and all analog circuitry is dis-
abled. When VCC reaches VPOA, the SEE is recalled,
and the analog circuitry is enabled. While VCC remains
above VPOA, the device is in its normal operating state,
and it responds based on its nonvolatile configuration.
If during operation VCC falls below VPOA but is still
above VPOD, the SRAM retains the SEE settings from
TX-F LATCHED OPERATION
TX-F NON LATCHED OPERATION
DETECTION OF
TX-F FAULT
TX-D OR
TX-F RESET
TX-F
DETECTION OF
TX-F FAULT
TX-F
Figure 5. TX-F Timing
Table 4. TX-F as a Function of TX-D and
Alarm Sources
VCC > VPOA
TX-D
NONMASKED
TX-F ALARM
TX-F
No
X
1
Yes
0
Yes
0
1
Yes
1
X
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLE8264E | IC SYSTEM BASIS CHIP DSO-36 |
| MAX4507CWN+T | IC SIGNAL LINE PROTECTOR 18-SOIC |
| TLE8263-2E | IC SYSTEM BASIS CHIP DSO-36 |
| TLE8263E | IC SYSTEM BASIS CHIP DSO-36 |
| TLE8262E | IC SYSTEM BASIS CHIP DSO-36 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1866 | 功能描述:數(shù)字電位計(jì) IC RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS1866+ | 功能描述:數(shù)字電位計(jì) IC Log Trimmer RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| DS1866S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| DS1866SN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。