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參數(shù)資料
| 型號： | DS1865T+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 44/67頁 |
| 文件大小： | 0K |
| 描述： | IC PON CONTROL TRI 28-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
| 類型： | * |
| 應(yīng)用： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
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DS1865
PON Triplexer Control and
Monitoring Circuit
____________________________________________________________________
49
Table 02h, Register 89h: Config
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
89h
FETG DIR
TX-F EN
RESERVED
ASEL
RESERVED
bit7
bit0
Configure the memory location and the polarity of the digital outputs.
bit7
FETG DIR: Chooses the direction or polarity of the FETG output for normal operation.
0 = (Default) Under normal operation, FETG is pulled low. Intended for use with nMOS.
1 = Under normal operation, FETG is pulled high. Intended for use with pMOS.
bit6
TX-F EN: The TX-F output pin always reflects the wired-OR of all TXF enabled alarm states. This bit
will enable the latching of the alarm state for the TXF output pin.
0 = (Default) Not latched.
1 = The alarm bits are latched until cleared by a TX-D transition or power-down. If VCC_Lo_Alarm is
enabled for either FETG or TX-F then latching is disabled until the after the first VCC measurement is
made above the VCC_Lo set point to allow for proper operation during slow power-on cycles.
bit5
RESERVED
bit4
ASEL: Address Select.
0 = (Default) Device Address of A2h.
1 = I2C slave address is determined by the value programmed in the DEVICE ADDRESS byte
(Table 02h, Register 8Ch).
bit3:0
RESERVED
Table 02h, Register 8Ah: Startup Step
FACTORY DEFAULT:
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
8Ah
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
bit7
bit0
This value will define the maximum allowed step for the upper 8 bits of IBIAS output during startup. Programming this value to 00h
cause the device to take single LSB (2
0) steps towards convergence. See the BIAS and MOD Output During Power-Up section for
details.
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