Table 02h" />
參數(shù)資料
型號: DS1865T+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 53/67頁
文件大?。?/td> 0K
描述: IC PON CONTROL TRI 28-TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
包裝: 帶卷 (TR)
DS1865
PON Triplexer Control and
Monitoring Circuit
____________________________________________________________________
57
Table 02h, Register B9h: FETG Enable0 (FETG EN0)
FACTORY DEFAULT
00h
READ ACCESS
PW2
WRITE ACCESS
PW2
MEMORY TYPE:
Nonvolatile (SEE)
B9h
HTXP EN
LTXP EN
BIAS-HI EN
BIAS MAX EN
RESERVED
bit7
bit0
Configures the maskable interrupt for the FETG pin.
bit7
HTXP EN: Enables/disables active interrupts on the FETG pin due to TXP fast comparisons above
the threshold limit.
0 = Disable (Default).
1 = Enable.
bit6
LTXP EN: Enables/disables active interrupts on the FETG pin due to TXP fast comparisons below
the threshold limit.
0 = Disable (Default).
1 = Enable.
bit5
BIAS HI EN: Enables/disables active interrupts on the FETG pin due to BIAS fast comparisons
above the threshold limit.
0 = (Default) Disable.
1 = Enable.
bit4
BIAS MAX EN: Enables/disables active interrupts on the FETG pin due to BIAS fast comparisons
below the threshold limit.
0 = (Default) Disable.
1 = Enable.
bit3:0
RESERVED (Default = 0)
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