參數(shù)資料
型號: DS1865T+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 27/67頁
文件大?。?/td> 0K
描述: IC PON CONTROL TRI 28-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
包裝: 帶卷 (TR)
DS1865
PON Triplexer Control and
Monitoring Circuit
____________________________________________________________________
33
Lower Memory, Register 6Eh: Status
POWER-ON VALUE
x000 0x0x b
READ ACCESS
All
WRITE ACCESS
See Below
MEMORY TYPE:
Volatile
Write Access
N/A
ALL
N/A
ALL
N/A
6Eh
FETG
STATUS
SOFT
FETG
RESERVED
TX-F
RESET
SOFT
TX-D
TX-F
STATUS
LOS
STATUS
RDYB
bit7
bit0
bit7
FETG STATUS: Reflects the active state of FETG. The FETG-DIR bit in Table 02h, Register 89h
defines the polarity of FETG.
0 = Normal operation. Bias and modulation outputs are enabled.
1 = The FETG output is active. Bias and modulation outputs are disabled.
bit6
SOFT FETG:
0 = (Default)
1 = Forces the bias and modulation outputs to their off states and asserts the FETG output.
bit5
RESERVED (Default = 0)
bit4
TX-F RESET:
0 = Does not affect the TX-F output. (Default)
1 = Resets the latch for the TX-F output. This bit is self-clearing after the reset.
bit3
SOFT TX-D: This bit allows a software control is identical to the TX-D pin. See the section on TX-D for
further information. Its value is wired-ORed with the logic value of the TX-D pin.
0 = Internal TX-D signal is equal to external TX-D pin.
1 = Internal TX-D signal is high.
bit2
TX-F STATUS: Reflects the active state of TX-F.
0 = TX-F pin is not active.
1 = TX-F pin is active.
bit1
LOS STATUS: Loss of Signal. Reflects the logic level of the D0 input pin. Note that with the use of the
MUX LOSI and INV LOSI bits (Table 02h, Register C0h), the D0 pin is controlled by the LOSI pin.
0 = D0 is logic-low.
1 = D0 is logic-high.
bit0
RDYB: Ready Bar.
0 = VCC is above POA.
1 = VCC is below POA or too low to communicate over the I2C bus.
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