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參數(shù)資料
| 型號： | DNC5X3125 |
| 廠商： | Lineage Power |
| 英文描述： | Gigabit Ethernet Transceiver Macrocell(千兆位以太網(wǎng)收發(fā)器宏單元) |
| 中文描述： | 千兆以太網(wǎng)收發(fā)器宏單元（千兆位以太網(wǎng)收發(fā)器宏單元） |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 260K |
| 代理商： | DNC5X3125 |
8
Lucent Technologies Inc.
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
Input/Output Information
Table 3a. I/O Channel Interface
Table 3b. I/O Control/PLL Interface Connections
Name
TX[9:0]
I/O
Input
Level
CMOS
Description
Transmit Data [9:0].
Parallel input bits [9:0], one 10-bit, 8b/
10b encoded data byte, clocked-in on the rising edge of TBC.
TX0 is the least significant bit.
Receive Data [9:0].
Parallel output bits [9:0], one 10-bit data
type, clocked-out on the alternate rising edges of RXCLK0,
RXCLK1. RX0 is the least significant bit.
Transmit Byte Clock (100 MHz—125 MHz).
Synchronous
with REFCLKN.
Receive Byte Clock 0.
Receive Byte Clock 1.
Enable Comma Detection.
Byte-Aligned Comma Detect.
Loopback at Serial I/O.
Lock Receiver to Clock.
Differential Serial Inputs.
Differential Serial Outputs.
Load TEST[5:1] Inputs.
RX[9:0]
Output
CMOS
TBC
Input
TTL/CMOS
RXCLK0
RXCLK1
ENCDET
COMDET
EWRAP
LCKREFN
HDINP HDINN
HDOUTP HDOUTN
LDST
Output
Output
Input
Output
Input
Input
Input
Output
Input
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
PECL
PECL
CMOS
Name
OLREF
OLRVS
LPWR
RESET
TEST5
TEST4
TEST3
TEST2
TEST1
BYPPLL
I/O
Level
Analog
Analog
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
PECL or TTL/
CMOS
CMOS
CMOS
CMOS
Description
Input/Output
Input/Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
PECL Level Set Resistor Terminal 1.
PECL Level Set Resistor Terminal 2.
Macrocell Low-Power Mode.
Macrocell Reset (Active-High).
Global Test Control Input.
Local Test Control Input.
Local Test Control Input.
Local Test Control Input.
Local Test Control Input.
Test Control—PLL Bypass Mode.
Reference Clock Input (100 MHz—125 MHz).
REFCLK, REFCLKN
PUR
PLLFB
ENPLLO
Input
Output
Output
Powerup Reset.
PLL Feedback Clock.
Enable PLL Feedback.
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