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參數(shù)資料
| 型號(hào)： | DNC5X3125 |
| 廠商： | Lineage Power |
| 英文描述： | Gigabit Ethernet Transceiver Macrocell(千兆位以太網(wǎng)收發(fā)器宏單元) |
| 中文描述： | 千兆以太網(wǎng)收發(fā)器宏單元（千兆位以太網(wǎng)收發(fā)器宏單元） |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 260K |
| 代理商： | DNC5X3125 |
17
Lucent Technologies Inc.
Advance Data Sheet
March 2000
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Test Modes
(continued)
Table 17. Test Modes
(continued)
Global
Local Test Configuration
Global
Operation
BYPPLL
0
Test1
0
Test2
0
Test3
1
Test4
0
Test5
Output
Transmitter is held in reset. BYPPLL
overrides this reset. Analog PLL feed-
back signal viewed at TEST5.
Transmitter and receiver are held in
reset. RX[9:0] output is from digital fil-
ter, not the serial data.
Transmitter and receiver are held in
reset. RX[9:0] output is from digital fil-
ter, not the serial data. Analog PLL
feedback signal viewed at TEST5.
Analog PLL is bypassed for low speed
functional test. A low speed clock is
input to TEST4, and a quadrature clock
is applied to TEST5. Frequency of
clocks is 5 x REFCLK, but here REF-
CLK is lowered to about 1 MHz.
Analog PLL is bypassed for low speed
functional test. A low speed clock is
input to TEST4, and a quadrature clock
is applied to TEST5. Frequency of
clocks is 5 x REFCLK, but here REF-
CLK is lowered to about 1 MHz.
RX[9:0] output is from digital filter, not
the serial data.
0
0
0
0
1
X
0
0
0
0
0
Output
1
X
X
1
C-0
C-90
1
X
X
0
C-0
C-90
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