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參數(shù)資料
| 型號： | DNC5X3125 |
| 廠商： | Lineage Power |
| 英文描述： | Gigabit Ethernet Transceiver Macrocell(千兆位以太網(wǎng)收發(fā)器宏單元) |
| 中文描述： | 千兆以太網(wǎng)收發(fā)器宏單元（千兆位以太網(wǎng)收發(fā)器宏單元） |
| 文件頁數(shù)： | 2/18頁 |
| 文件大小： | 260K |
| 代理商： | DNC5X3125 |
2
Table of Contents
Lucent Technologies Inc.
Contents
Page
Table
Page
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
Overview .....................................................................1
Features.......................................................................1
Functional Description ................................................3
Transmitter Section.................................................. 3
Receiver Section..................................................... 3
Lock to Reference ....................................................3
Byte Alignment .........................................................4
Parallel Output Port ................................................. 4
Loopback Mode Operation ......................................4
Powerup Sequence .................................................5
Macrocell Reset .......................................................5
Sleep Mode ..............................................................5
Block Diagrams ........................................................6
Input/Output Information .............................................8
Electrical Specifications ..............................................9
Transmitter ...............................................................9
Receiver .................................................................10
Timing Characteristics ..............................................11
Serial Timing ..........................................................11
Receiver Section Timing ........................................12
Receiver Port Timing..............................................12
Transmitter Section Timing.................................... 13
Application Information ............................................. 14
Test Modes ...............................................................16
Figure
Page
Figure 1. Quad Gigabit Ethernet Transceiver
Block Diagram.............................................. 6
Figure 2. DNC5X3125 Single-Channel Transceiver
Functional Block Diagram ........................... 7
Figure 3. Serial Interface Timing............................... 11
Figure 4. Receiver Section Timing............................ 12
Figure 5. Receiver Port Timing ................................ 12
Figure 6. Parallel Interface Transmit Timing ............. 13
Figure 7. Reference Clock Connections with
Single-Ended Source................................. 14
Figure 8. Typical Termination for a Single-Channel,
High-Speed, Serial Transmit and Receive
Port in a 50
Backplane Application ........ 14
Figure 9. Typical Termination for a Single-Channel,
High-Speed Serial Transmit/Receive Port
Interfacing a 5 V GBIC Transceiver............ 15
Table 1. Receive Circuit Operating Modes.................. 3
Table 2. Definition of Bit Transmission/
Reception Order............................................ 4
Table 3a. I/O Channel Interface .................................. 8
Table 3b. I/O Control/PLL Interface Connections ....... 8
Table 3c. Power Connections ..................................... 9
Table 4. Reference Clock Specifications (REFCLK
and REFCLKN)............................................. 9
Table 5. PLL Specifications ........................................ 9
Table 6. Output Jitter at 1.0 Gbits/s—1.25 Gbits/s ..... 9
Table 7. Receive Input Data Rate ............................. 10
Table 8. Data Lock Characteristics ........................... 10
Table 9. Power Dissipation ....................................... 10
Table 10. dc Electrical Specifications ....................... 10
Table 11. Absolute Maximum Ratings ...................... 10
Table 12. Serial Output Timing Levels ...................... 11
Table 13. Serial Input Interface Timing ..................... 11
Table 14. Receiver Parallel Port Timing ................... 12
Table 15. Transmitter Timing at Parallel Interface ..... 13
Table 16. External Resistor Value vs. Differential
Output Level Viewing ................................ 15
Table 17. Test Modes ............................................... 16
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