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參數(shù)資料
| 型號： | DNC5X3125 |
| 廠商： | Lineage Power |
| 英文描述： | Gigabit Ethernet Transceiver Macrocell(千兆位以太網(wǎng)收發(fā)器宏單元) |
| 中文描述： | 千兆以太網(wǎng)收發(fā)器宏單元（千兆位以太網(wǎng)收發(fā)器宏單元） |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 260K |
| 代理商： | DNC5X3125 |
16
Lucent Technologies Inc.
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
Test Modes
Note:
Test modes are intended for manufacture test only and are not guaranteed to be operational. They may be
modified or eliminated without prior notice.
The device has per-channel test modes as well as global test modes. The bypass PLL, BYPPLL, is a global test
input because it modifies the operation of the analog PLL. Test bits TEST[4:1] generally operate in the localized
mode. The LDST[A:D] inputs are enable signals that permit the TEST[4:1] signals to be injected into a particular
channel.
For example, if LDST = 1, the TEST[4:1] signals directly control the test modes in the A channel. Once LDST = 0,
the previous values of TEST[4:1] are held for the A channel. The TEST[4:1] signals control the four channels (A, B,
C, D) via level sense latches that are gated with the LDST[A:D] inputs. TEST[5] is a global test node used for both
injection of signals as well as for monitoring points within the device.
Table 17. Test Modes
Global
Local Test Configuration
Global
Operation
BYPPLL
0
0
Test1
1
1
Test2
1
1
Test3
1
1
Test4
1
0
Test5
X
Output
Normal operation.
Analog PLL feedback signal viewed at
TEST5.
Transceiver operates normally except
RX[9:0] output is from digital filter, not
the serial data.
Transceiver operates normally except
RX[9:0] output is from digital filter and
the analog PLL feedback signal is
viewed at TEST5.
Digital filter forced to count. Pulses
applied at TEST4 increments accumu-
lator, pulses at TEST5 decrements
accumulator.
RX[9:0] output is from digital filter, not
the serial data. Digital filter forced to
count. Pulses applied at TEST4 incre-
ments accumulator, pulses at TEST5
decrements accumulator.
Parallel loopback. TX[9:0] = RX[9:0].
RX[9:0] remains active.
Parallel loopback. TX[9:0] = RX[9:0]
and analog PLL feedback signal viewed
at TEST5. RX[9:0] remains active.
RX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.
RX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.
Analog PLL feedback signal viewed at
TEST5.
Transmitter is held in reset. BYPPLL
overrides this reset.
0
1
1
0
1
X
0
1
1
0
0
Output
0
1
0
1
P
P
0
1
0
0
P
P
0
0
1
1
1
X
0
0
1
1
0
Output
0
0
1
0
1
X
0
0
1
0
0
Output
0
0
0
1
1
X
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