參數(shù)資料
型號： DM9161E
廠商： Electronic Theatre Controls, Inc.
英文描述： 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
中文描述： 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器
文件頁數(shù)： 7/47頁
文件大?。?/td> 561K
代理商： DM9161E
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final 7
Version: DM9161-DS-F02
May 10,2002
34
RXCLK
/SCRAMEN
/10BTSER
O,
Z,
LI
(U)
Receive Clock
The received clock provides the timing reference for the transfer of the
RXDV, RXD, and RXER. RXCLK is provided by PHY. The PHY may
recover the RXCLK reference from the received data or it may derive the
RXCLK reference from a nominal clock
25MHz in 100Mbps MII mode, 2.5MHz in 10Mbps MII mode, 10MHz in
10Mbps GPSI (7-Wired) mode
SCRAMEN 10BTSER only support for forced 100M mode or 10M mode;
not support for auto-negotiation mode (power up reset latch input)
0 = Bypass scramble in 100M mode, GPSI (7-Wired) mode in 10M mode
1 = Enable scramble (default) in 100M mode, MII mode in 10M mode
Carrier Sense Detect/ PHYAD[4]
Asserted high to indicate the presence of carrier due to receive or transmit
activities in half-duplex mode of 10BASE-T or 100BASE-TX. In repeater
mode or full-duplex mode, this signal is asserted high to indicate the
presence of carrier due to receive activity only
This pin is also used as PHYAD [4] (power up reset latch input)
PHY address sensing input pin
Collision Detection
Asserted high to indicate the detection of the collision conditions in half-
duplex mode of 10Mbps and 100Mbps. In full-duplex mode, this signal is
always logical 0
Reduced MII enable:
This pin is also used to select Normal MII or Reduced MII. (power up reset
latch input)
0= Normal MII (default)
1= Reduced MII
This pin is always pulled low except used as reduced MII
Receive Data Valid
Asserted high to indicate that the valid data is presented on the RXD [0:3]
Test mode control pin (power up reset latch input)
0 = normal operation (default)
1 = enable test mode
Receive Data Error/The Fifth RXD Data Bit of the 5B Symbol
Asserted high to indicate that an invalid symbol has been detected
In decoder bypass mode (bypass BP4B5B), RXER becomes RXD [4], the
fifth RXD data bit of the 5B symbol
This pin is also used to select Repeater or Node mode. (power up reset
latch input)
0 = Node Mode (default)
1 = Repeater Mode
Receive Enable
Active high enables receive signals RXD [0:3], RXCLK, RXDV and RXCLK.
Active low on this input tri-states these output pins. In node application, this
pin should be pulled high. In repeater application, this pin may be connected
to a repeater controller
Reset
Active low input that initializes the DM9161.
35
CRS
/PHYAD[4]
O,
Z,
LI
(D)
36
COL
/RMII
O,
Z,
LI
(D)
37
RXDV
/TESTMODE
O,
Z,
LI
(D)
38
RXER/RXD[4]
/RPTR
O,
Z,
LI
(D)
31
RXEN
I
40
RESET#
I
相關(guān)PDF資料
PDF描述
DM9301 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
DM9301F 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
DM9324 5-Bit Comparator
DM9324N 5-Bit Comparator
DM9328 Dual 8-Bit Shift Register
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9161EP 制造商:DAVICOM 功能描述:IC TRX 10/100MBPS ENET PHY48LQFP 制造商:DAVICOM 功能描述:IC, TRX, 10/100MBPS, ENET PHY,48LQFP 制造商:DAVICOM 功能描述:CONTROLLER, ETHERNET, 100MBPS, LQFP-48; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Max:3.3V; Digital IC Case Style:LQFP; No. of Pins:48; IC Interface Type:MII, RMII; Package / Case:48-LQFP ;RoHS Compliant: Yes
DM9161電路圖-1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DM9161電路圖-1
DM9162 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DM9162EP 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DM9162NP 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*