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參數(shù)資料
| 型號(hào)： | DM9161E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| 中文描述： | 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 24/47頁 |
| 文件大小： | 561K |
| 代理商： | DM9161E |
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
24
Final
Version: DM9161-DS-F02
May 10,2002
1 = Valid link is established (for either 10Mbps or 100Mbps operation)
0 = Link is not established
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the link status bit to be
cleared and remain cleared until it is read via the management
interface
Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions will
set this bit unless it is cleared by a read to this register through a
management interface or a DM9161 reset. This bit works only in
10Mbps mode
Extended Capability
1 = Extended register capable
0 = Basic register capable only
1.1
Jabber detect
0, RO/LH
1.0
Extended
capability
1,RO/P
8.3 PHY ID Identifier Register #1 (PHYID1) - 02
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9161. The Identifier consists of
a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision
number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
Bit Name
OUI_MSB
Default
<0181h>
Description
2.15-2.0
OUI Most Significant Bits
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2)
8.4 PHY ID Identifier Register #2 (PHYID2) - 03
Bit
Bit Name
OUI_LSB
Default
<101110>,
RO/P
Description
3.15-3.10
OUI Least Significant Bits
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
Vendor Model Number
Six bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
Model Revision Number
Four bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 3)
3.9-3.4
VNDR_MDL
<001000>,
RO/P
3.3-3.0
MDL_REV
<0001>,
RO/P
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9161EP | 制造商:DAVICOM 功能描述:IC TRX 10/100MBPS ENET PHY48LQFP 制造商:DAVICOM 功能描述:IC, TRX, 10/100MBPS, ENET PHY,48LQFP 制造商:DAVICOM 功能描述:CONTROLLER, ETHERNET, 100MBPS, LQFP-48; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Max:3.3V; Digital IC Case Style:LQFP; No. of Pins:48; IC Interface Type:MII, RMII; Package / Case:48-LQFP ;RoHS Compliant: Yes |
| DM9161電路圖-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DM9161電路圖-1 |
| DM9162 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9162EP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9162NP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
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