- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376803 > DM9161E (Electronic Theatre Controls, Inc.) 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER PDF資料下載
參數(shù)資料
| 型號： | DM9161E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| 中文描述： | 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 29/47頁 |
| 文件大?。?/td> | 561K |
| 代理商： | DM9161E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final 29
Version: DM9161-DS-F02
May 10,2002
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Bit
17.15
Bit Name
100FDX
Default
1, RO
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If
this bit is 1, it means the operation 1 mode is a 100M full duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If
this bit is 1, it means the operation 1 mode is a 100M half duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If
this bit is 1, it means the operation 1 mode is a 10M Full Duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If
this bit is 1, it means the operation 1 mode is a 10M half duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
Reserved
Read as 0, ignore on write
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple
PHY entities must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
written to these bits
17.14
100HDX
1, RO
17.13
10FDX
1, RO
17.12
10HDX
1, RO
17.11-
17.9
17.8-17.4
Reserved
0, RO
PHYADR[4:0]
(PHYADR),
RW
17.3-17.0
ANMB[3:0]
0, RO
B3 b2 b1 B0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal_link_ready
Parallel detects signal_link_ready fail
Auto-negotiation completed successfully
相關PDF資料 |
PDF描述 |
|---|---|
| DM9301 | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |
| DM9301F | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |
| DM9324 | 5-Bit Comparator |
| DM9324N | 5-Bit Comparator |
| DM9328 | Dual 8-Bit Shift Register |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DM9161EP | 制造商:DAVICOM 功能描述:IC TRX 10/100MBPS ENET PHY48LQFP 制造商:DAVICOM 功能描述:IC, TRX, 10/100MBPS, ENET PHY,48LQFP 制造商:DAVICOM 功能描述:CONTROLLER, ETHERNET, 100MBPS, LQFP-48; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Max:3.3V; Digital IC Case Style:LQFP; No. of Pins:48; IC Interface Type:MII, RMII; Package / Case:48-LQFP ;RoHS Compliant: Yes |
| DM9161電路圖-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DM9161電路圖-1 |
| DM9162 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9162EP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9162NP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復。