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參數(shù)資料
| 型號： | DM9161E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
| 中文描述： | 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器 |
| 文件頁數(shù)： | 12/47頁 |
| 文件大?。?/td> | 561K |
| 代理商： | DM9161E |
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
12
Final
Version: DM9161-DS-F02
May 10,2002
7. Functional Description
The DM9161 Fast Ethernet single chip transceiver, providing
the functionality as specified in IEEE 802.3u, integrates a
complete 100Base-TX module and a complete 10Base-T
module. The DM9161 provides a Media Independent
Interface (MII) as defined in the IEEE 802.3u standard
(Clause 22).
The DM9161 performs all PCS (Physical Coding Sublayer),
PMA (Physical Media Access), TP-PMD (Twisted Pair
Physical
Medium
Dependent)
Encoder/Decoder, and Twisted Pair Media Access Unit
(TPMAU) functions. Figure 1 shows the major functional
blocks implemented in the DM9161.
sublayer,
10Base-T
MII Interface
100Base-TX
Transmitter
100Base-TX
Receiver
10Base-T
Tranceiver
Carrier
Sense
Collision
Detection
Auto
Negotiation
MII Serial
Management
Interface
Figure 7-1
7.1 MII Interface
The DM 9161 provides a Media Independent Interface (MII)
as defined in the IEEE 802.3u standard (Clause 22).
The purpose of the MII interface is to provide a simple, easy
to implement connection between the MAC Reconciliation
layer and the PHY. The MII is designed to make the
differences between various media transparent to the MAC
sublayer.
The MII consists of a nibble wide receive data bus, a nibble
wide transmit data bus, and control signals to facilitate data
transfers between the PHY and the Reconciliation layer.
TXD (transmit data) is a nibble (4 bits) of data that are
driven by the reconciliation sublayer synchronously with
respect to TXCLK. For each TXCLK period, which
TXEN is asserted, TXD (3:0) are accepted for
transmission by the PHY.
TXCLK (transmit clock) output to the MAC reconciliation
sublayer is a continuous clock that provides the timing
reference for the transfer of the TXEN, TXD, and TXER
signals.
TXEN (transmit enable) input from the MAC
reconciliation sublayer indicates that nibbles are being
presented on the MII for transmission on the physical
medium.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9161EP | 制造商:DAVICOM 功能描述:IC TRX 10/100MBPS ENET PHY48LQFP 制造商:DAVICOM 功能描述:IC, TRX, 10/100MBPS, ENET PHY,48LQFP 制造商:DAVICOM 功能描述:CONTROLLER, ETHERNET, 100MBPS, LQFP-48; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Max:3.3V; Digital IC Case Style:LQFP; No. of Pins:48; IC Interface Type:MII, RMII; Package / Case:48-LQFP ;RoHS Compliant: Yes |
| DM9161電路圖-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DM9161電路圖-1 |
| DM9162 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9162EP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| DM9162NP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
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