參數(shù)資料
型號: DM9161E
廠商: Electronic Theatre Controls, Inc.
英文描述: 10/100 Mbps FAST ETHERNET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
中文描述: 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器
文件頁數(shù): 21/47頁
文件大小: 561K
代理商: DM9161E
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Final 21
Version: DM9161-DS-F02
May 10,2002
8. MII Register Description
ADD
00
Name
CONTROL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
Loop
back
TX FDX
Cap.
Speed
select
TX HDX
Cap.
Auto-N
Enable
10
FDX
Cap.
0
1
Reserved
Power
Down
10 HDX
Cap.
Isolate Restart
Auto-N
Reserved
Full
Duplex
Coll.
Test
Reserved
01
STATUS
T4
Cap.
Pream.
Supr.
Auto-N
Compl.
Remote
Fault
Auto-N
Cap.
Link
Status
Jabber
Detect
Extd
Cap.
02
03
04
PHYID1
PHYID2
Auto-Neg.
Advertise
Link Part.
Ability
Auto-Neg.
Expansion
Aux.
Config.
Aux.
Conf/Stat
10T
Conf/Stat
MDINTR
0
1
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0
0
0
0
Model No.
TX HDX
Adv
LP
TX HDX
Version No.
Next
Page
LP Next
Page
FLP Rcv
Ack
LP
Ack
Remote
Fault
LP
RF
FC
Adv
LP
FC
T4
Adv
LP
T4
TX FDX
Adv
LP
TX FDX
10 FDX
Adv
LP
10 FDX
10 HDX
Adv
LP
10 HDX
Advertised Protocol Selector Field
05
Reserved
Link Partner Protocol Selector Field
06
Reserved
Pardet
Fault
RPDCT
R-EN
LP Next
Pg Able
Reset
St. Mch
Next Pg
Able
Pream.
Supr.
Auto-N. Monitor Bit [3:0]
New Pg
Rcv
Sleep
mode
LP AutoN
Cap.
Remote
LoopOut
16
BP
4B5B
100
FDX
Rsvd
BP
SCR
100
HDX
LP
Enable
Rsvd
BP
ALIGN
10
FDX
HBE
Enable
Rsvd
BP_A
DPOK
10
HDX
SQUE
Enable
Rsvd
Repeat
mode
TX
Select
Reserved
Rsvd
RMII
Enable
Force
100LNK
PHY ADDR [4:0]
SPDLE
D_CTL
COLLE
D_CTL
17
18
JAB
Enable
FDX
Mask
10T
Serial
SPD
Mask
Reserved
Polarity
Reverse
INTR
Status
21
INTR
PEND
Link
Mask
INTR
Mask
Rsvd
Rsvd
Rsvd
FDX
Change
SPD
Change
Link
Change
Rsvd
22
Rcv Error
Counter
Disconnect
Counter
Rstlh
Stat
Receive Error Counter
23
Reserved
Disconnect Counter
24
0
0
LH_
ISO
LH_
CSTS
LH_
RMII
LH_
SCRAM
LH_
REP
LH_
T5TMOD
LH_OP [2:0]
LH_PHYAD [4:0}
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where
<Reset Value>:
1
0
X
(PIN#)
Bit set to logic one
Bit set to logic zero
No default value
Value latched in from pin # at reset
<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
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