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參數(shù)資料
| 型號： | DM9102DE |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| 中文描述： | 單晶片快速以太網(wǎng)NIC控制器 |
| 文件頁數(shù)： | 51/70頁 |
| 文件大?。?/td> | 2245K |
| 代理商： | DM9102DE |
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Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
51
7.5 Power Management
7.5.1 Overview
The DM9102D supports power management mechanism. It
complies with the ACPI Specification Rev 1.0, the Network
Device Class Power Management Specification Rev 1.0,
and the PCI Bus Power Management Interface
Specification Rev 1.0. In addition, it also supports the
Wake-On LAN (WOL) which is the feature of the AMD’s
Magic Packet technology. With this function, it can
wakeup a remote sleeping station.
7.5.2 PCI Function Power Management States
The DM9102D supports PCI function power states D0,
D3(hot), D3(cold), and does not support D1, D2 states. In
addition, PCI signals PME# (power management event,
open drain) to pin A19 of the standard PCI connector.
D0:
normal & fully functional state
D3 (hot):
For controller, configuration space, that can be
accessed and wake up on LAN circuit, can be enabled.
PME# operational circuit is active, full function is supported
to detect the wake up Frame & Link status. Because of
functions in D3(hot) must respond to configuration space
accesses as long as power and clock are supplied so that
they can be returned to D0 state by software.
D3 (cold):
If Vcc is removed from a PCI device, all of its PCI
functions transition immediately to D3(cold), no bus
transaction is active without pci_clk condition and wake up
on LAN operation should be alive. PME# operational circuit
is active. Full function is supported under auxiliary power to
detect the magic packet & Link status. When power
restored, PCI RST# must be asserted and functions will
return to D0 with a full PCI Spec. 2.2 compliant power-on
reset sequence. The power required in D3(cold) must be
provided by some auxiliary power source.
7.5.3 The Power Management Operation
It complies with the PCI Bus Power Management Interface
Specification Rev. 1.0. The Power Management Event
(PME#) signal is an optional open drain, active low signal
that is intended to be driven low by a PCI function to request
a change in its current power management state and/or to
indicate that a power management event has occurred.
The PME# signal has been assigned to pin A19 of the
standard PCI Connector configuration. The assertion and
de-assertion of PME# is asynchronous to the PCI clock.
Software will enable its use by setting the PME_En bit in the
PMCSR (write 1 to PMCSR<8>). When a PCI function
generates or detects an event that requires the system to
change its power state, the function will assert PME#. It
must continue to assert PME# until software either clears
the PME_En bit (PMCSR<8> is set to 0) or clears the
PME_Status bit in the PMCSR (write 1 to PMCSR<15>).
DM9102D supports three main categories of network device
wake up events specified in Network Device Class Power
Management Rev1.0. That is, the DM9102D can monitor
the network for a Link Change, Magic Packet or a Wake-up
Frame and notify the system by generating PME# if any of
the three events occurs. Programming the PCIUSR (offset =
40h) can select the PME# event, and writing 1 to
PMCSR<15> will clear the PME#.
a. Detect Network Link State Change
Any link status change will set the wake up event.
1. Writes 1 into PMCSR<15>(54h) to clear previous PME#
status
2. Writes 1 into PMCSR<8> to enable PME# function
3. Writes 1 into PCIUSR<29> to enable the link status
change function
b. Active Magic Packet Function
It can be enabled by PCIUSR<27> or optionally enabled by
EEPROM setting. The magic node address stored at node
address table can use setup frame perfect address filtering
mode or loading from EEPROM WORD 10~12 after power
on .
1. Writes 1 into PMCSR<15> to clear previous PME status
2. Writes 1 into PMCSR<8> to enable PME# function
3. Writes 1 into PCIUSR<27> to enable magic packet
function.
c. Active the Sample Frame Function
It can be enabled by PCIUSR<28>. Sample frame data and
corresponding byte mask are loaded into transmit FIFO &
receive FIFO before entering D3(hot). The software driver
has to stop the TX/RX process before setting the sample
frame and byte mask into the FIFO. Transmit & receive
FIFO can be accessed from CR13 & CR14 by
programming CR6<28:25> = 0011.
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| DM9102DEP | 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes |
| DM9102H | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9102HEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9103 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface |
| DM9103EP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Three Port Ethernet Switch Controller with PCI Interface |
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