參數(shù)資料
型號: DM9102DE
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)NIC控制器
文件頁數(shù): 37/70頁
文件大小: 2245K
代理商: DM9102DE
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
37
Write as 0, ignore on read
0, RO/LH Local Device Parallel Detection Fault:
PDF=1: A fault detected via parallel detection function.
PDF=0: No fault detected via parallel detection function
0, RO
Link Partner Next Page Able:
LP_NP_ABLE=1: Link partner, next page available
LP_NP_ABLE=0: Link partner, no next page
0,RO/P
Local Device Next Page Able:
NP_ABLE=1: DM9102D, next page available
NP_ABLE=0: DM9102D, no next page
DM9102D does not support this function, so this bit is always 0.
0, RC/LH New Page Received:
A new link of code-word page received. This bit will be automatically cleared
when the register (Register 6) is read by management.
0, RO
Link Partner Auto-negotiation Able:
A “1” in this bit indicates that the link partner supports Auto-negotiation.
4
PDF
3
LP_NP_ABLE
2
NP_ABLE
1
PAGE_RX
0
LP_AN_ABLE
6.3.8 DAVICOM Specified Configuration Register (DSCR) – 10H
Bit
Name
15
BP_4B5B
Default
0,RW
Description
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and symbol
decoding functions) bypassed. Transmit functions (symbol encoder
and scrambler) bypassed
0 = Normal operation
Reserved
Reserved
Reserved
Force Good Link in 100Mbps:
1 = Force 100Mbps good link status
0 = Normal 100Mbps operation
This bit is useful for diagnostic purposes.
Reserved
Reduced Power Down Control Mode:
This bit is used to enable automatic reduced power down
1 = Enable automatic reduced power down
0 = Disable automatic reduced power down
Reset State Machine:
When writes 1 to this bit, all state machines of PHY will be reset. This bit is
self-clear after reset is completed.
MF Preamble Suppression Control:
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
14
BP_SCR
0, RW
13
BP_ALIGN
0, RW
12:11
10
9:8
7
Reserved
Reserved
Reserved
F_LINK_100
0, RW
1, RW
0, RW
0, RW
6:5
4
Reserved
RPDCTR_EN
00,RW
1,RW
3
SMRST
0,RC
2
MFPSC
1,RW
相關(guān)PDF資料
PDF描述
DM9102 Single Chip Fast Ethernet NIC controller
DM9102A Single Chip Fast Ethernet NIC controller
DM9102AF Single Chip Fast Ethernet NIC controller
DM9102AT Single Chip Fast Ethernet NIC controller
DM9108APPLICATIONENGINEERINGNOTESONE DM9108 Application Engineering notes one
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參數(shù)描述
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