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| 型號： | DM9102DE |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| 中文描述： | 單晶片快速以太網(wǎng)NIC控制器 |
| 文件頁數(shù)： | 41/70頁 |
| 文件大小： | 2245K |
| 代理商： | DM9102DE |
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Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
41
7. Functional Description
7.1 System Buffer Management
7.1.1 Overview
The data buffers for reception and the transmission of data
reside in the host memory. They are addressd by the
descriptor list that is also located in another region of the
host memory. All actions for the buffer management are
operated by the DM9102D in conjunction with the software
driver. The data structures and processing algorithms are
described in the following text.
7.1.2 Data Structure and Descriptor List
There are two types of buffers that reside in the host
memory, the transmit buffer and the receive buffer. The
buffers are composed of many distributed regions in the
host memory. They are linked together and controlled by the
descriptor lists that reside in another region of the host
memory. The descriptor list is a chain structure. The content
of each descriptor includes pointer to the buffer, size of the
buffer, command and status for the packet to be transmitted
or received. Each descriptor list starts from the address
setting of CR3 (receive descriptor base address) and CR4
(transmit descriptor base address). Refer to Figure 7-1.
7.1.3 Buffer Management -- Chain Structure Method
As the Chain structure depicted below, each descriptor
contains two pointers, one point to a single buffer and the
other to the next descriptor chained. The first descriptor is
chained to the last descriptor under host driver’s control to
form a looped chain. With this structure, a descriptor can be
allocated anywhere in host memory and is chained to the
next descriptor.
Buffer 1
Buffer 1
Descriptor 1
Descriptor N
Packet N
control
buffer address 1
status
own
not valid
next descriptor address
buffer 1 length
Figure 7-1
7.1.4 Descriptor List: Buffer Descriptor Format
(a). Receive Descriptor Format
Each receive descriptor has four double word entries and
may be read or written by the host or the DM9102D. The
descriptor format is shown below with a detailed functional
description.
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相關(guān)代理商/技術(shù)參數(shù) |
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| DM9102DEP | 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes |
| DM9102H | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9102HEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9103 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface |
| DM9103EP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Three Port Ethernet Switch Controller with PCI Interface |
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