參數(shù)資料
型號: DM9102DE
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)NIC控制器
文件頁數(shù): 47/70頁
文件大?。?/td> 2245K
代理商: DM9102DE
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
47
7.2 Initialization Procedure
After hardware or software reset, transmit and receive
processes are placed in the state of STOP. The DM9102D
can accept the host commands to start operation. The
general procedure for initialization is described below:
(1) Read/write suitable values for the PCI configuration
registers.
(2) Write CR3 and CR4 to provide the starting address of
each descriptor list.
(3) Write CR0 to set global host bus operation parameters.
(4) Write CR7 to mask causes of unnecessary interrupt.
(5) Write CR6 to set global parameters and start both
receive and transmit processes. Receive and transmit
processes will enter the running state and attempt to acquire
descriptors from the respective descriptor lists.
(6) Wait for any interrupt.
7.2.1 Data Buffer Processing Algorithm
The data buffer process algorithm is based on the
cooperation of the host and the DM9102D. The host sets
CR3 (receive descriptor base address) and CR4 (transmit
descriptor base address) for the descriptor list initialization.
The DM9102D will start the data buffer transfer after the
descriptor polling and get the ownership. For detailed
processing procedure, please see below.
7.2.2 Receive Data Buffer Processing
Refer to Figure 7-2. The DM9102D always attempts to
acquire an extra descriptor in anticipation of the incoming
frames. Any incoming frame size covers a few buffer
regions and descriptors. The following conditions satisfy the
descriptor acquisition attempt:
When start/stop receive sets immediately after being placed
in the running state.
When the DM9102D begins writing frame data to a data
buffer pointed to by the current descriptor and the buffer
ends before the frame ends.
When the DM9102D completes the reception of a frame
and the current receiving descriptor is closed.
When receive process is suspended due to no free buffer
for the DM9102D and a new frame is received.
When receive polling demand is issued. After acquiring the
free descriptor, the DM9102D processes the incoming
frame and places it in the acquired descriptor's data buffer.
When the whole received frame data has been transferred,
the DM9102D will write the status information to the last
descriptor. The same process will repeat until it encounters a
descriptor flagged as being owned by the host. If this occurs,
receive process enters the suspended state and waits the
host to service
Receive Buffer Management State Transition
Figure 7-2
FIFO Threshold
Reached
Stop
State
Descriptor
Access
Data
Transfer
Write
Status
Suspended
Start Receive Command or
Receive Poll Command
Buffer Available
( OWN bit = 1 )
Frame Fully
Received
Buffer not
RecUnavailabl
New Frame Coming or
Receive Poll Command
Stop Receive Command or Reset Command
Buffer Full
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