- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄20411 > DM300023 (Microchip Technology)KIT DEMO DSPICDEM SMPS BUCK PDF資料下載
參數(shù)資料
| 型號： | DM300023 |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 124/285頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEMO DSPICDEM SMPS BUCK |
| 特色產(chǎn)品： | SMPS & Digital Power Conversion Solutions |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | dsPIC™ |
| 主要目的： | DC/DC，步降 |
| 輸出及類型： | 2，非隔離 |
| 輸入電壓： | 7 ~ 15 V |
| 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu)： | 降壓 |
| 板類型： | 完全填充 |
| 已供物品： | 板，軟件 |
| 已用 IC / 零件： | dsPIC30F2020 |
| 產(chǎn)品目錄頁面： | 659 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | DSPIC30F2020-30I/MMB32-ND - IC DSPIC MCU/DSP 12K 28QFN DSPIC30F2020T-30I/SODKR-ND - IC DSPIC MCU/DSP 12K 28SOIC DSPIC30F2020T-30I/SOCT-ND - IC DSPIC MCU/DSP 12K 28SOIC DSPIC30F2020-20E/MM-ND - IC DSPIC MCU/DSP 12K 28QFN DSPIC30F1010-30I/SP-ND - IC DSPIC MCU/DSP 6K 28DIP DSPIC30F1010-30I/SO-ND - IC DSPIC MCU/DSP 6K 28SOIC DSPIC30F1010-30I/MM-ND - IC DSPIC MCU/DSP 6K 28QFN DSPIC30F1010-20E/SP-ND - IC DSPIC MCU/DSP 6K 28DIP DSPIC30F1010-20E/SO-ND - IC DSPIC MCU/DSP 6K 28SOIC DSPIC30F2020-20E/SO-ND - IC DSPIC MCU/DSP 12K 28SOIC 更多... |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁當(dāng)前第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁第279頁第280頁第281頁第282頁第283頁第284頁第285頁
2006 Microchip Technology Inc.
Preliminary
DS70178C-page 19
dsPIC30F1010/202X
2.0
CPU ARCHITECTURE
OVERVIEW
2.1
Core Overview
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (see Section 3.1 “Program
Address Space”), and the Most Significant bit (MSb)
is ignored during normal program execution, except for
certain specialized instructions. Thus, the PC can
address up to 4M instruction words of user program
space. An instruction prefetch mechanism is used to
help maintain throughput. Program loop constructs,
free from loop count management overhead, are sup-
ported using the DO and REPEAT instructions, both of
which are interruptible at any point.
The working register array consists of 16x16-bit regis-
ters, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software Stack Pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Genera-
tion Unit (AGU). Most instructions operate solely
through the X memory AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2 “Data Address Space”). The X and Y
data space boundary is device-specific and cannot be
altered by the user. Each data word consists of 2 bytes,
and most instructions can address data either as words
or bytes.
There are two methods of accessing data stored in
program memory:
The upper 32 Kbytes of data space memory can be
mapped into the lower half (user space) of program
space at any 16K program word boundary, defined
by the 8-bit Program Space Visibility Page
(PSVPAG) register. This lets any instruction access
program space as if it were data space, with a limita-
tion that the access requires an additional cycle.
Moreover, only the lower 16 bits of each instruction
word can be accessed using this method.
Linear indirect access of 32K word pages within
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
Overhead-free circular buffers (modulo addressing)
are supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports Bit-Reversed Addressing
mode on destination effective addresses, to greatly
simplify input or output data reordering for radix-2 FFT
algorithms. Refer to Section 4.0 “Address Generator
Units” for details on modulo and Bit-Reversed
Addressing.
The core supports Inherent (no operand), Relative, Lit-
eral, Memory Direct, Register Direct, Register Indirect,
Register Offset and Literal Offset Addressing modes.
Instructions are associated with predefined Addressing
modes, depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A + B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high-speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumula-
tor or any working register can be shifted up to 15 bits
right or 16 bits left in a single cycle. The DSP instruc-
tions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by
dedicating certain working registers to each address
space for the MAC class of instructions.
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction prefetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle, with certain
exceptions.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user-assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest) in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities, ranging from 8 to 15.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 345-062-524-204 | CARDEDGE 62POS DUAL .100 GREEN |
| GBM11DRTI-S13 | CONN EDGECARD 22POS .156 EXTEND |
| T95D477M6R3HSSS | CAP TANT 470UF 6.3V 20% 2917 |
| 345-062-524-202 | CARDEDGE 62POS DUAL .100 GREEN |
| RJZ-1224S | CONV DC/DC 2W 12VIN 24VOUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM300024 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC dsPICDEM 1.1 GP RoHS:否 制造商:Microchip Technology 產(chǎn)品:Starter Kits 工具用于評估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
| DM300027 | 功能描述:開發(fā)板和工具包 - PIC / DSPIC 16-bit Starter Demo Board RoHS:否 制造商:Microchip Technology 產(chǎn)品:Starter Kits 工具用于評估:chipKIT 核心:Uno32 接口類型: 工作電源電壓: |
| DM-3-000-K | 制造商:PacTec 功能描述:Case, Plastic; ABS; Black; 11.46 in.; 3.38 in.; 10.4 in.; UL 94-HB Rated 制造商:PacTec 功能描述:ENCLOSURE, DESKTOP, PLASTIC, BLACK; Enclosure Type:Desktop; Enclosure Material:Plastic; Body Color:Black; External Height - Imperial:3.38"; External Height - Metric:86mm; External Width - Imperial:10.4"; External Width - Metric:264mm;RoHS Compliant: Yes |
| DM-300-C | 制造商:Greenlee Textron Inc 功能描述:DMM 1000V RMS |
| DM-301 | 制造商:Labfacility Limited 功能描述:SENSOR PT100 THIN FILM 2X2.3MM CL B 制造商:LABFACILITY 功能描述:SENSOR, PT100, THIN FILM, 2X2.3MM, CL B 制造商:LABFACILITY 功能描述:TEMPERATURE RTD SENSOR, -70C to +500C, 100 OHM; Sensing Temperature Min:-70C; Sensing Temperature Max:+500C; Resistance:100ohm; Sensor Terminals:Through Hole; Temperature Sensing Range:-70C to +500C ;RoHS Compliant: Yes |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。