參數(shù)資料
型號: DEMO9RS08KA2
廠商: Freescale Semiconductor
文件頁數(shù): 72/136頁
文件大小: 0K
描述: DEMO BOARD FOR 9RS08KA2
產(chǎn)品培訓(xùn)模塊: Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標(biāo)準(zhǔn)包裝: 1
系列: RS08
類型: MCU
適用于相關(guān)產(chǎn)品: MC9RS08KA2
所含物品: 板,線纜,CD,文檔,樣品 IC
產(chǎn)品目錄頁面: 730 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: MC9RS08KA2CSCRTR-ND - IC MCU 8BIT 2K FLASH 8-SOIC
PC9RS08KA2PAE-ND - MCU 8BIT 2KB FLASH RS08 8-DIP
PC9RS08KA2FPE-ND - MCU 8BIT 2KB FLASH RS08 6-VDFN
PC9RS08KA2DWE-ND - MCU 8BIT 2KB FLASH RS08 8-SOIC
MC9RS08KA2CPC-ND - IC MCU 8-BIT 2K FLASH 8-PDIP
MC9RS08KA2CDB-ND - IC MCU 8-BIT 2K FLASH 6-DFN
MC9RS08KA2CSC-ND - IC MCU 8-BIT 2K FLASH 8-SOIC
Chapter 5 Resets, Interrupts, and General System Control
MC9RS08KA2 Series Data Sheet, Rev. 4
40
Freescale Semiconductor
5.8.3
System Device Identification Register (SDIDH, SDIDL)
These high page read-only registers are included so host development systems can identify the RS08
derivative and revision number. This allows the development software to recognize where specific
memory blocks, registers, and control bits are located in a target MCU.
1. The revision number that is hard coded into these bits reflects the current silicon revision level.
Figure 5-3. System Device Identification Register — High (SDIDH)
Table 5-3. SOPT Register Field Descriptions
Field
Description
7
COPE
COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6
COPT
COP Watchdog Timeout — This write-once bit selects the timeout period of the COP.
0 Short timeout period selected.
1 Long timeout period selected.
5
STOPE
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
1
BKGDPE1,2
1 When the device is reset into normal operating mode (MS is high during reset), BKGDPE is reset to 1 if Flash security is
disengaged (SECD = 1); BKGDPE is reset to 0 if Flash security is engaged (SECD = 0). When the device is reset into active
BDM mode (MS is low during reset), BKGDPE is always reset to 1 such that BDM communication is allowed.
2 BKGDPE can only write once from value 1 to 0. Writing from value 0 to 1 by user software is not allowed. BKGDPE can be
changed back to 1 only by a POR or reset with proper condition as stated in Note 1.
Background Debug Mode Pin Enable — This write-once bit when set enables the PTA3/ACMPO/BKGD/MS
pin to function as BKGD/MS. When clear, the pin functions as one of its output only alternative functions. This
pin defaults to the BKGD/MS function following any MCU reset.
0 PTA3/ACMPO/BKGD/MS pin functions as PTA3 or ACMPO.
1 PTA3/ACMPO/BKGD/MS pin functions as BKGD/MS.
0
RSTPE
RESET Pin Enable — When set, this write-once bit enables the PTA2/KBIP2/TCLK/RESET/VPP pin to function
as RESET. When clear, the pin functions as one of its input-only alternative functions. This pin is input-only port
function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on RESET.
0 PTA2/KBIP2/TCLK/RESET/VPP pin functions as PTA2/KBIP2/TCLK/VPP.
1 PTA2/KBIP2/TCLK/RESET/VPP pin functions as RESET/VPP.
76
54
321
0
R
W
Reset:
0 (Note 1)
1
0
= Unimplemented or Reserved
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