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| 型號(hào)： | DEMO9RS08KA2 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 3/136頁(yè) |
| 文件大小： | 0K |
| 描述： | DEMO BOARD FOR 9RS08KA2 |
| 產(chǎn)品培訓(xùn)模塊： | Mechatronics USBSpyder08 Discovery Kit RS08KA2 Low-End Microcontroller Series MC9RS08KA8 Microcontroller |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | RS08 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | MC9RS08KA2 |
| 所含物品： | 板，線纜，CD，文檔，樣品 IC |
| 產(chǎn)品目錄頁(yè)面： | 730 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | MC9RS08KA2CSCRTR-ND - IC MCU 8BIT 2K FLASH 8-SOIC PC9RS08KA2PAE-ND - MCU 8BIT 2KB FLASH RS08 8-DIP PC9RS08KA2FPE-ND - MCU 8BIT 2KB FLASH RS08 6-VDFN PC9RS08KA2DWE-ND - MCU 8BIT 2KB FLASH RS08 8-SOIC MC9RS08KA2CPC-ND - IC MCU 8-BIT 2K FLASH 8-PDIP MC9RS08KA2CDB-ND - IC MCU 8-BIT 2K FLASH 6-DFN MC9RS08KA2CSC-ND - IC MCU 8-BIT 2K FLASH 8-SOIC |
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Chapter 12 Development Support
MC9RS08KA2 Series Data Sheet, Rev. 4
100
Freescale Semiconductor
The BDC serial communication protocol requires the host to know the target BDC clock speed.
Commands and data are sent most significant bit first (MSB-first) at 16 BDC clock cycles per bit. The
interface times out if 512 BDC clock cycles occur between falling edges from the host. Any BDC
command that was in progress when this timeout occurs is aborted without affecting the memory or
operating mode of the target MCU system.
Figure 12-3 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target MCU. The host
is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where
the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the
bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during
host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin
during the host-to-target period, there is no need to treat the line as an open-drain signal during this period.
Figure 12-3. BDC Host-to-Target Serial Bit Timing
Figure 12-4 shows the host receiving a logic 1 from the target MCU. Because the host is asynchronous to
the target, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived
start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize
it (at least two target BDC cycles). The host must release the low drive before the target drives a brief
active-high speedup pulse seven cycles after the perceived start of the bit time. The host must sample the
bit level approximately 10 cycles after it started the bit time.
EARLIEST START
TARGET SENSES BIT LEVEL
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
BDC CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED START
OF BIT TIME
OF NEXT BIT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DEMO9RS08KA8 | 功能描述:開(kāi)發(fā)板和工具包 - S08 / S12 DEMO BOARD FOR KA8 PRODUCT RoHS:否 產(chǎn)品:Development Kits 工具用于評(píng)估:MC9S12G128 核心:S12 接口類型:CAN, LIN, RS-232, USB 工作電源電壓:5 V 制造商:Freescale Semiconductor |
| DEMO9RS08KB12 | 功能描述:開(kāi)發(fā)板和工具包 - S08 / S12 KB12 DEMO Board RoHS:否 產(chǎn)品:Development Kits 工具用于評(píng)估:MC9S12G128 核心:S12 接口類型:CAN, LIN, RS-232, USB 工作電源電壓:5 V 制造商:Freescale Semiconductor |
| DEMO9RS08KB12 | 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE |
| DEMO9RS08LA8 | 功能描述:開(kāi)發(fā)板和工具包 - S08 / S12 DEMO BOARD FOR LA8 RoHS:否 產(chǎn)品:Development Kits 工具用于評(píng)估:MC9S12G128 核心:S12 接口類型:CAN, LIN, RS-232, USB 工作電源電壓:5 V 制造商:Freescale Semiconductor |
| DEMO9RS08LE4 | 功能描述:開(kāi)發(fā)板和工具包 - S08 / S12 LE4 Family Demo Board RoHS:否 產(chǎn)品:Development Kits 工具用于評(píng)估:MC9S12G128 核心:S12 接口類型:CAN, LIN, RS-232, USB 工作電源電壓:5 V 制造商:Freescale Semiconductor |
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