參數(shù)資料
型號: DEMO9RS08KA2
廠商: Freescale Semiconductor
文件頁數(shù): 116/136頁
文件大?。?/td> 0K
描述: DEMO BOARD FOR 9RS08KA2
產(chǎn)品培訓(xùn)模塊: Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標準包裝: 1
系列: RS08
類型: MCU
適用于相關(guān)產(chǎn)品: MC9RS08KA2
所含物品: 板,線纜,CD,文檔,樣品 IC
產(chǎn)品目錄頁面: 730 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: MC9RS08KA2CSCRTR-ND - IC MCU 8BIT 2K FLASH 8-SOIC
PC9RS08KA2PAE-ND - MCU 8BIT 2KB FLASH RS08 8-DIP
PC9RS08KA2FPE-ND - MCU 8BIT 2KB FLASH RS08 6-VDFN
PC9RS08KA2DWE-ND - MCU 8BIT 2KB FLASH RS08 8-SOIC
MC9RS08KA2CPC-ND - IC MCU 8-BIT 2K FLASH 8-PDIP
MC9RS08KA2CDB-ND - IC MCU 8-BIT 2K FLASH 6-DFN
MC9RS08KA2CSC-ND - IC MCU 8-BIT 2K FLASH 8-SOIC
Internal Clock Source (RS08ICSV1)
MC9RS08KA2 Series Data Sheet, Rev. 4
80
Freescale Semiconductor
9.4
Functional Description
9.4.1
Operational Modes
The states of the ICS are shown as a state diagram and are described in this section. The arrows indicate
the allowed movements between the states.
Figure 9-7. Clock Switching Modes
9.4.1.1
FLL Engaged Internal (FEI)
FLL engaged internal (FEI) is the default mode of operation out of any reset and is entered when CLKS is
written to 0.
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency.
9.4.1.2
FLL Bypassed Internal (FBI)
The FLL bypassed internal (FBI) mode is entered when CLKS is written to 1 and LP bit is a 0.
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 512
times the filter frequency.
9.4.1.3
FLL Bypassed Internal Low Power (FBILP)
The FLL bypassed internal low power (FBILP) mode is entered when CLKS is written to 1 and LP = 1.
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock
and the FLL is disabled.
FLL Bypassed
Internal Low
Power(FBILP)
CLKS=0
1 ICS enters its Stop state when MCU enters stop, FLL is always disabled. ICS returns to the state that
was active before MCU entered stop, unless a reset occurs while in stop.
2 If IREFSTEN is set when MCU enters stop, the ICSIRCLK remains running.
FLL Engaged
Internal (FEI)
FLL Bypassed
Internal (FBI)
CLKS=1
LP=0
CLKS=1
LP=1
Stop1, 2
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