參數(shù)資料
型號: DEMO9RS08KA2
廠商: Freescale Semiconductor
文件頁數(shù): 54/136頁
文件大?。?/td> 0K
描述: DEMO BOARD FOR 9RS08KA2
產(chǎn)品培訓(xùn)模塊: Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標(biāo)準(zhǔn)包裝: 1
系列: RS08
類型: MCU
適用于相關(guān)產(chǎn)品: MC9RS08KA2
所含物品: 板,線纜,CD,文檔,樣品 IC
產(chǎn)品目錄頁面: 730 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: MC9RS08KA2CSCRTR-ND - IC MCU 8BIT 2K FLASH 8-SOIC
PC9RS08KA2PAE-ND - MCU 8BIT 2KB FLASH RS08 8-DIP
PC9RS08KA2FPE-ND - MCU 8BIT 2KB FLASH RS08 6-VDFN
PC9RS08KA2DWE-ND - MCU 8BIT 2KB FLASH RS08 8-SOIC
MC9RS08KA2CPC-ND - IC MCU 8-BIT 2K FLASH 8-PDIP
MC9RS08KA2CDB-ND - IC MCU 8-BIT 2K FLASH 6-DFN
MC9RS08KA2CSC-ND - IC MCU 8-BIT 2K FLASH 8-SOIC
Chapter 3 Modes of Operation
MC9RS08KA2 Series Data Sheet, Rev. 4
24
Freescale Semiconductor
the IREFSTEN bit. For the ICS to run in stop, the LVDE and LVDSE bits in the SPMSC1 must both be
set before entering stop.
3.6.1
Active BDM Enabled in Stop Mode
Entry into active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This
register is described in the Development Support chapter of this data sheet. If ENBDM is set when the CPU
executes a STOP instruction, the system clocks to the background debug logic remain active when the
MCU enters stop mode so background debug communication is still possible. In addition, the voltage
regulator does not enter its low-power standby state; it maintains full internal regulation.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After active background mode is entered, all background
commands are available.
Table 3-3 summarizes the behavior of the MCU in stop when entry into the active background mode is
enabled.
3.6.2
LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, the voltage regulator remains active.
Table 3-4 summarizes the behavior of the MCU in stop when LVD reset is enabled.
Table 3-3. BDM Enabled Stop Mode Behavior
Mode
CPU
Digital
Peripherals
ICS
ACMP
Regulator
I/O Pins
RTI
Stop
Standby
On
Optionally
on
On
States held
Optionally on
Table 3-4. LVD Enabled Stop Mode Behavior
Mode
CPU
Digital
Peripherals
ICS
ACMP
Regulator
I/O Pins
RTI
Stop
Standby
Optionally
on
Optionally
on
On
States held
Optionally on
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