參數(shù)資料
型號: DEMO9RS08KA2
廠商: Freescale Semiconductor
文件頁數(shù): 136/136頁
文件大?。?/td> 0K
描述: DEMO BOARD FOR 9RS08KA2
產(chǎn)品培訓(xùn)模塊: Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標(biāo)準(zhǔn)包裝: 1
系列: RS08
類型: MCU
適用于相關(guān)產(chǎn)品: MC9RS08KA2
所含物品: 板,線纜,CD,文檔,樣品 IC
產(chǎn)品目錄頁面: 730 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: MC9RS08KA2CSCRTR-ND - IC MCU 8BIT 2K FLASH 8-SOIC
PC9RS08KA2PAE-ND - MCU 8BIT 2KB FLASH RS08 8-DIP
PC9RS08KA2FPE-ND - MCU 8BIT 2KB FLASH RS08 6-VDFN
PC9RS08KA2DWE-ND - MCU 8BIT 2KB FLASH RS08 8-SOIC
MC9RS08KA2CPC-ND - IC MCU 8-BIT 2K FLASH 8-PDIP
MC9RS08KA2CDB-ND - IC MCU 8-BIT 2K FLASH 6-DFN
MC9RS08KA2CSC-ND - IC MCU 8-BIT 2K FLASH 8-SOIC
Chapter 12 Development Support
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
99
Figure 12-2. Standard RS08 BDM Tool Connector
Background debug controller (BDC) serial communications use a custom serial protocol that was first
introduced on the M68HC12 Family of microcontrollers. This protocol requires that the host knows the
communication clock rate, which is determined by the target BDC clock rate. If a host is attempting to
communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to
the target MCU to request a timed sync response signal from which the host can determine the correct
communication speed.
For RS08 MCUs, the BDC clock is the same frequency as the MCU bus clock. For a detailed description
of the communications protocol, refer to Section 12.3.2, “Communication Details."
12.3.1
BKGD Pin Description
BKGD is the single-wire background debug interface pin. BKGD is a pseudo-open-drain pin that contains
an on-chip pullup, therefore it requires no external pullup resistor. Unlike typical open-drain pins, the
external resistor capacitor (RC) time constant on this pin, which is influenced by external capacitance,
plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup
pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to
The primary function of this pin is bidirectional serial communication of background debug commands
and data. During reset, this pin selects between starting in active background mode and normal user mode
running an application program. This pin is also used to request a timed sync response pulse to allow a
host development tool to determine the target BDC clock frequency.
By controlling the BKGD pin and forcing an MCU reset (issuing a BDC_RESET command, or through a
power-on reset (POR)), the host can force the target system to reset into active background mode rather
than start the user application program. This is useful to gain control of a target MCU whose FLASH
program memory has not yet been programmed with a user application program.
When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD
determines the normal operating mode.
On some RS08 devices, the BKGD pin may be shared with an alternative output-only function. To support
BDM debugging, the user must disable this alternative function. Debugging of the alternative function
must be done in normal user mode without using BDM.
12.3.2
Communication Details
The BDC serial interface requires the host to generate a falling edge on the BKGD pin to indicate the start
of each bit time. The host provides this falling edge whether data is transmitted or received.
2
4
6
5
3
1
RESET/VPP
BKGD
GND
V
DD
NO CONNECT
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