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參數(shù)資料
| 型號： | DEM-VSP2232Y |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS |
| 中文描述： | CCD信號處理器的數(shù)碼相機(jī) |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 248K |
| 代理商： | DEM-VSP2232Y |
VSP2232
SLAS320
–
MAY 2001
8
www.ti.com
detailed description (continued)
standby mode
For the purpose of power saving, the VSP2232 can be set into the standby mode (or power down mode) through
the serial interface when the VSP2232 is not in use. Refer to
serial interface
for details. In this mode, all the
function blocks are disabled and the digital outputs will go to all zeros. The consumption current will drop to
2 mA. As all the bypass capacitors will discharge during this mode, a substantial time (usually of the order of
200 ms to 300 ms) is required to restore from the standby mode.
voltage reference
All the reference voltages and bias currents needed in the VSP2232 are generated by its internal bandgap
circuitry. The CDS and the ADC use three reference voltages, REFP (positive reference, pin 38), REFN
(negative reference, pin 39), and CM (common-mode voltage, pin 37). All of REFP, REFN, and CM should be
heavily decoupled with appropriate capacitors (for example: 0.1-
μ
F ceramic capacitor). Do not use these
voltages anywhere else in the system because it affects the stability of these reference levels, and causes ADC
performance degradation. These are analog output pins, so do not apply the voltage from the outside.
BYPP2 (pin 29), BYP (pin 31), and BYPM (pin 32) are also reference voltages to be used in the analog circuit.
BYP should be connected to the ground with a 0.1-
μ
F ceramic capacitor. The capacitor value for BYPP2 and
BYPM affects the step response. We consider, for many applications, 200 pF to 600 pF is the reasonable value.
However, it depends on the application environment, and making careful adjustments using the cut-and-try
method is recommended. All of BYPP2, BYP, and BYPM should be heavily decoupled with appropriate
capacitors. Do not use these voltages anywhere else in the system because it affects the stability of these
reference levels, and causes the performance degradation. These are analog output pins, so do not apply the
voltage from the outside.
additional output delay control
The VSP2232 can control delay time of the output data by register setting through the serial interface. In some
cases, the transition of the output data affects analog performance. Generally, it is avoided by adjusting the
timing of the ADCCK. In case ADCCK timing cannot be adjusted, this output delay control is effective to reduce
the influence of transient noise. Refer to
serial interface
for details.
serial interface
The serial interface has a 2-byte shift register and various parallel registers to control all the digitally
programmable features of the VSP2232. Writing to these registers is controlled by four signals (SLOAD, SCLK,
SDATA, and RESET). To enable the shift register, SLOAD must be pulled low. SDATA is the serial data input
and the SCLK is the shift clock. The data at SDATA is taken into the shift register at the rising edge of SCLK.
The data length should be 2 bytes. After the 2-byte shift operation, the data in the shift register will be transferred
to the parallel latch at the rising edge of SLOAD. In addition to the parallel latch, there are several registers
dedicated to the specific features of the device and they are synchronized with the ADCCK clock. It takes five
or six clock cycles for the data in the parallel latch to be written to those registers. Thus, to complete the data
updates, it has to wait five or six clock cycles after the parallel latching by the rising edge of SLOAD.
The serial interface data format is shown in Table 2. TEST is the flag for the test mode (Burr-Brown proprietary
only), A0 to A2 is the address for the various registers, and D0 to D11 is the data or the operand field.
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