參數(shù)資料
型號(hào)： DEM-VSP2232Y
廠商： Texas Instruments, Inc.
英文描述： CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS
中文描述： CCD信號(hào)處理器的數(shù)碼相機(jī)
文件頁(yè)數(shù)： 10/19頁(yè)
文件大?。?/td> 248K
代理商： DEM-VSP2232Y
VSP2232
SLAS320
–
MAY 2001
10
www.ti.com
timing
VSP2232 has two options to drive the on-chip A/D converter. The internal drive mode and the external drive
mode can be selected by accessing the configuration register via the serial interface. The internal drive mode,
the drive clock for the A/D converter, is generated by the on-chip timing control circuit automatically, based on
the SHP and SHD signals. The external drive mode is the master clock (ADCCK) and drives the on-chip A/D
converter directly. The digital data output is synchronized with the master clock (ADCCK) and it is independent
from the drive mode.
The CDS and the ADC are operated by SHP/SHD and their derivative timing clocks generated by the on-chip
timing generator. The digital output data is synchronized with ADCCK. The timing relationship among the CCD
signal, SHP/SHD, ADCCK, and the output data is shown in the VSP2232 CDS timing specifications. CLPOB
is used to activate the black-level clamp loop during the OB pixel interval, and CLPDM is used to activate the
input clamping during the dummy pixel interval. If the CLPDM pulse is not available in your system, the CLPOB
pulse can be used in place of CLPDM as long as the clamping takes place during black pixels, refer to
input
clamp and dummy pixel clamp
for details. The clock polarities of SHP/SHD, CLPOB, and CLPDM can be
independently set through the serial interface, refer to
serial interface section
for details. The description and
the timing diagrams in this data sheet are all based on the polarity of active low (default value). In order to keep
a stable and accurate OB clamp level, it is recommended that CLPOB should not be activated during the PBLK
active period. Refer to
preblanking and data latency
for details. In the standby mode, ADCCK, SHP, SHD,
CLPOB, and CLPDM are internally masked and pulled high.
power supply, grounding, and device decoupling recommendations
The VSP2232 incorporates a very high-precision and high-speed analog-to-digital converter and analog
circuitry that are vulnerable to any extraneous noise from the rails or elsewhere. For this reason, although the
VSP2232 has analog and digital supply pins, it should be treated as an analog component and all supply pins
except for DRV
DD
should be powered by only the analog supply of the system. This will ensure the most
consistent results, since digital power lines often carry high levels of wide band noise that would otherwise be
coupled into the device and degrade the achievable performance.
Proper grounding, short lead length, and the use of ground planes are also very important for high frequency
designs. Multilayer PC boards are recommended for the best performance since they offer distinct advantages
like minimizing ground impedance, separation of signal layers by ground layers, etc. It is highly recommended
that the analog and digital ground pins of the VSP2232 be joined together at the IC and be connected only to
the analog ground of the system. The driver stage of the digital outputs (B(11:0]) is supplied through a dedicated
supply pin (DRV
DD
) and should be separated from the other supply pins completely, or at least with a ferrite
bead. It is also recommended to keep the capacitive loading on the output data lines as low as possible (typically
less than 15 pF). Larger capacitive loads demand higher charging current due to surges that can feed back into
the analog portion of the VSP2232 and affect the performance.
If possible, external buffers or latches should be used which provide the added benefit of isolating the VSP2232
from any digital noise activities on the data lines. In addition, resistors in series with each data line may help
in minimizing the surge current. Values in the range of 100
to 200
will limit the instantaneous current to the
output stage and has to provide for recharging the parasitic capacitance
’
s as the output levels change from
low-to-high or high-to-low. Because of the high operation speed, the converter also generates high frequency
current transients and noises that are fed back into the supply and reference lines. This requires the supply and
reference pins to be sufficiently bypassed. In most cases, a 0.1-
μ
F ceramic-chip capacitor is adequate to
decouple the reference pins. Supply pins should be decoupled to the ground plane with a parallel combination
of tantalum (1
μ
F to 22
μ
F) and ceramic (0.1
μ
F) capacitors. The effectiveness of the decoupling largely depends
on the proximity to the individual pin. DRV
DD
should be decoupled to the proximity of DRVGND. Special
attention must be paid to the bypassing of COB, BYPP2, and BYPM since these capacitor values determine
important analog performance of the device.
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