- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376632 > DEM-VSP2232Y (Texas Instruments, Inc.) CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS PDF資料下載
參數(shù)資料
| 型號： | DEM-VSP2232Y |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS |
| 中文描述： | CCD信號處理器的數(shù)碼相機 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 248K |
| 代理商： | DEM-VSP2232Y |
VSP2232
SLAS320
–
MAY 2001
5
www.ti.com
correlated double sampler (CDS) (continued)
Also, an off-chip emitter follower buffer is recommended that can drive more than 10 pF, because the 5 pF of
the sampling capacitor and a few pF of stray capacitance can be seen at the input pin. The analog input signal
range at the CCDIN pin is 1 V
P
–
P
, and the appropriate common mode voltage for the CDS is around 0.5 V to
1.5 V.
The reference level is sampled during SHP active period, and the voltage level is held on the sampling capacitor
C
(1)
at the trailing edge of SHP. The data level is sampled during SHD active period, and the voltage level is
held on the sampling capacitor C
(2)
at the trailing edge of SHD. Then, the switched-capacitor amplifier performs
the subtraction of these two levels.
The active polarity of SHP/SHD (active high or active low) can be chosen through the serial interface, refer to
serial interface
for details. The default value of SHP/SHD is active low. However, right after power on, this value
is unknown. For this reason, it must be set to the appropriate value by using the serial interface, or reset to the
default value by the RESET pin. The description and the timing diagrams in this data sheet are all based on the
polarity of active low (default value).
input clamp and dummy pixel clamp
The buffered CCD output is capacitively coupled to the VSP2232. The purpose of the input clamp is to restore
the dc component of the input signal that was lost with the ac-coupling and establish the desired dc bias point
for the CDS. Figure 1 shows the simplified block diagram of the input clamp. The input level is clamped to the
internal reference voltage REFN (1.25 V) during the dummy pixel interval. More specifically, when both CLPDM
and SHP are active, then the dummy clamp function becomes active. If the dummy pixels and/or the CLPDM
pulse are not available in your system, the CLPOB pulse can be used in place of CLPDM as long as the clamping
takes place during black pixels. In this case, both CPLDM pin (actives as same timing as CLPOB) and SHP
become active during the optical black pixel interval, then the dummy clamp function becomes active.
The active polarity of CLPDM and SHP (active high or active low) can be chosen through the serial interface,
refer to
serial interface
for details. The default value of CLPDM and SHP is active low. However, right after power
on, this value is unknown. For this reason, it must be set to the appropriate value by using the serial interface,
or reset to the default value by the RESET pin. The description and timing diagrams in this data sheet are all
based on the polarity of active low (default value).
high performance analog-to-digital converter (ADC)
The analog-to-digital converter (ADC) utilizes a fully differential and pipelined architecture. This ADC is well
suited for low voltage operation, low power consumption requirement, and high-speed applications. It assures
10-bit resolution of the output data with no missing code. The VSP2232 includes the reference voltage generator
for the ADC. REFP (positive reference, pin 38), REFN (negative reference, pin 39), and CM (common-mode
voltage, pin 37) should be bypassed to the ground with a 0.1-
μ
F ceramic capacitor. Do not use this voltage
anywhere else in the system because it affects the stability of these reference levels, and then causes ADC
performance degradation. These are analog output pins, so do not apply voltage from the outside.
programmable gain amplifier (PGA)
Figure 2 shows the characteristics of the PGA gain. The PGA provides a gain range of
–
6 dB to 42 dB, which
is linear in dB. The gain is controlled by a digital code with 10-bit resolution, and it can be settle through the serial
interface, refer to the serial interface section for details. The default value of the gain control code is 128 (PGA
gain = 0 dB). However, right after power on, this value is unknown. For this reason, it must be set to the
appropriate value by using the serial interface, or reset to the default value by the RESET pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DEM16101H | LCD MODULE |
| DEM16101SYH | DEM16101SYH |
| DEM16216SYH-LY | DEM16216SYH-LY |
| DEM16216SYH-PY | Display Elektronik GmbH |
| DEM16217SYH | Display Elektronik GmbH |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DEM-VSP2260Y | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DEM-VSP2262Y | 制造商:Texas Instruments 功能描述:EVAL BD FOR CCD SGNL PROCESSOR FOR DGTL CAMERAS - Bulk |
| DEM-VSP3100Y | 制造商:Texas Instruments 功能描述:EVALUATION/DEMO BOARD FOR VSP3100Y - Bulk |
| DEMX-5W1P-1AON-K87 | 制造商:ITT Interconnect Solutions 功能描述:DEMX-5W1P-1AON-K87 - Bulk |
| DEMX5W1PK87 | 制造商:ITT 功能描述:DSUB 5W1 M PCR/A G50 T 制造商:ITT Interconnect Solutions 功能描述:DSUB 5W1 M PCR/A G50 T |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。