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參數(shù)資料
| 型號(hào)： | DEM-VSP2232Y |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS |
| 中文描述： | CCD信號(hào)處理器的數(shù)碼相機(jī) |
| 文件頁(yè)數(shù)： | 15/19頁(yè) |
| 文件大?。?/td> | 248K |
| 代理商： | DEM-VSP2232Y |
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VSP2232
SLAS320
–
MAY 2001
15
www.ti.com
timing specifications (continued)
N
N+1
N+2
N+3
tw(P)
tp(P
–
D)
tw(D)
tp(D
–
P)
ts
t(AP)
t(CKP)
t(CKP)
ts
t(ADC)
t(ADC)
t(CKP)
t(HOLD)
t(OD)
N
–
11
N
–
10
N
–
9
N
–
8
N
–
7
CCDD
Output
Signal
SHP
See Note 1
SHD
See Note 1
B(0
–
9)
ADCCK
PARAMETER
MIN
TYP
MAX
UNIT
t(CKP)
t(ADC)
tw(P)
tw(D)
tp(P
–
D)
tp(D
–
P)
ts
t(AP)
t(Hold)
t(OD)
Clock period
27.7
ns
ADCCK pulse duty rate
45%
50%
55%
SHP pulse width
6.9
ns
SHD pulse width
6.9
ns
SHP trailing edge to SHD leading edge (see Note 8)
1
ns
SHD trailing edge to SHP leading edge (see Note 8)
6
ns
Sampling delay
3
ns
ADCCK leading edge to SHP trailing edge
0
1.5
ns
Output hold time (see Note 9)
2
ns
Output delay
27.7
ns
DL
Data latency, normal operation mode
9(fixed)
Clock
cycles
NOTES:
8. The description and the timing diagrams in this data sheet are all based on the polarity of active low (default value). The active polarity
(active low or active high) can be chosen through the serial interface, refer to
serial interface
for details.
9. Output hold time is specified at additonal output delay = 0 ns. Refer to serial interface section for detail.
Figure 4. VSP2232 CDS Timing Specifications
—
A/D Converter External Drive Mode
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