參數(shù)資料
型號： DDP3310B
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分類： 消費(fèi)家電
英文描述： Display and Deflection Processor
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 6/60頁
文件大?。?/td> 1540K
代理商： DDP3310B
DDP 3310B
ADVANCE INFORMATION
6
Micronas
2. Functional Description
2.1. Display Part
The display part converts the digital YC
r
C
b
to analog
RGB (see Fig. 2
–
7) and provides contrast and satura-
tion adjustment. In case of YC
r
C
b
4:1:1 an interpola-
tion filter is used, which converts the digital input signal
to YC
r
C
b
4:2:2 standard. The 4:2:2 YC
r
C
b
signal is
processed by the horizontal scaler. In the luminance
processing path, a variety of features, such as
dynamic peaking and soft limiting, are provided. In the
chrominance path, the C
r
C
b
signals are converted to
4:4:4 format and filtered by a color transient improve-
ment circuit. The YC
r
C
b
signal is converted by a pro-
grammable matrix to RGB color space.
2.1.1. Input Interface
The data inputs Y0
…
Y7 and C0
…
C7 are clocked with
the external clock LLC2. The clock frequency is select-
able for 27 or 32 MHz. A clock generator converts the
different external line-locked clock rates to a common
internal sample rate of appr. 40.5 MHz in order to pro-
vide a fix bandwidth for all digital filters. The horizontal
scaler is used for conversion of scan rate and non-lin-
ear aspect ratio. The horizontal sync puls at the HS pin
should be an active video signal, which is not vertically
blanked.
The input interface signals are
–
external clock (LLC2)
–
luma / chroma inputs (Y0
…
Y7 / C0
…
C7)
–
horizontal sync (HS) / vertical sync (VS, VS2)
2.1.2. Horizontal Scaler
The scaler block allows linear or non-linear horizontal
scaling of the digital input video signal in the range of
0.25 to 4. Non-linear scaling, also called
“
panorama
vision
”
, provides a geometrical distortion of the input
picture. It is used to fit a picture with 4:3 format on a
16:9 screen by stretching the picture geometry at the
borders. The inverse effect can be produced by the
scaler, also. The scaler consists of a programmable
decimation and interpolation filter and a 1/2H FIFO
memory.
A summary of scaler modes is given in Table 2
–
1.
2.1.3. Luma Processing
The blacklevel of the input signal is assumed to be 16
(ITU-R standard). The luminance signal is multiplied
by a factor between 0 and 2 subdivided into 64 steps.
With a contrast adjustment of 32 (gain
=
1) the signal
can be shifted by
±
100 % of its maximal amplitude with
the digital brightness value. This is for adjustment of
the headrooms for under- and overshoot. After the
brightness addition, the negative going signals are lim-
ited to zero. It is desirable to keep a small positive off-
set with the signal to prevent undershoots produced by
the peaking from being cut.
Table 2
–
1:
Scaler modes
Mode
Scale
Factor
Description
Panorama
4:3
→
16:9
non-
linear
compr.
4:3 source displayed on
a16:9 tube,
borders distorted
Waterglass
16:9
→
4:3
non-
linear
zoom
Letterbox source (PAL+)
displayed on a 4:3 tube,
vertical overscan,
borders distorted,
no cropping
27
→
40.5 MHz
1.5
linear
sample rate conversion
from external to internal
pixel clock
32
→
40 MHz
1.25
linear
sample rate conversion
from external to internal
pixel clock
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