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參數(shù)資料
| 型號： | DDP3310B |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | Display and Deflection Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 21/60頁 |
| 文件大?。?/td> | 1540K |
| 代理商： | DDP3310B |
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ADVANCE INFORMATION
DDP 3310B
Micronas
21
3. Serial Interface
3.1. I
2
C-Bus Interface
Communication between the DDP 3310B and the
external controller is done via I
2
C-bus. The
DDP 3310B has an I
2
C-bus slave interface and uses
I
2
C clock synchronization to slow down the interface if
required.
Basically, there are two classes of registers in the
DDP 3310B:
1. The first class are directly addressable I
2
C registers.
They are embedded in the hardware. These regis-
ters are 8 or 16 bit wide.
2. The second class are
“
XDFP-REGISTERS
”
, which
are used by the
“
XDFP
”
on-chip controller. These
registers are all 16 bit wide and read- and writable.
Communication with these registers requires I
2
C
packets with a 16-bit XDFP-register address and
16-bit data.
Communication with both classes of registers (I
2
C and
XDFP-REGISTERS) are performed via I
2
C; but the for-
mat of the I
2
C telegram depends on which type of reg-
ister is being accessed.
The I
2
C-bus chip address of the DDP 3310B is given
below:
3.2. I
2
C
Control and Status Registers
The I
2
C-bus interface uses one level of subaddress.
First, the bus address selects the IC, then a subad-
dress selects one of the internal registers. They have
8- or 16-bit data size; 16-bit registers are accessed by
reading/writing two 8-bit data words.
–
Writing is done by sending the device address first
followed by the subaddress byte and one or two
data bytes.
–
For reading, the read address has to be transmitted
first by sending the device write address, followed
by the subaddress, a second start condition with the
device read address, and reading one or two bytes
of data.
Fig. 3
–
2 shows I
2
C protocol for read and write opera-
tions; the read operation requires an extra start condi-
tion and repetition of the chip address with read com-
mand set. Table 3
–
2 gives definitions of the I
2
C control
and status registers.
Fig. 3
–
1:
I
2
C-Bus protocol (MSB first, data must be stable while clock is High)
Fig. 3
–
2:
I
2
C-Bus protocol
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
0
1
0
1
1/0
SDA
SCL
1
0
S
P
I
2
C-Bus Start Condition
I
2
C-Bus Stop Condition
S
P
=
=
Nak
Ack
S
1000 101 W Ack
Sub-Addr.
Ack S
1000 101
Ack
R
High-Byte Data
Low-Byte Data
1- or 2-Byte Data
S
1000 101 W Ack Sub-Addr. Ack
Ack
P
P
Write to I
2
C Control Register :
Read from I
2
C Control Register :
Start Condition
Stop Condition
W
R
Ack
Nak
S
P
=
=
1 (Read Bit)
0 (Write Bit)
=
=
=
=
0 (Acknowledge Bit from DDP 3310B=gray
or controller=hatched)
1 (Not Acknowledge Bit from controller=hatched
indicating an error state from DDP 3310B=gray)
or
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