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參數(shù)資料
| 型號： | DDP3310B |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | Display and Deflection Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 40/60頁 |
| 文件大?。?/td> | 1540K |
| 代理商： | DDP3310B |
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DDP 3310B
ADVANCE INFORMATION
40
Micronas
Pin 63
–
Sync Signal Input
HS
(Fig. 4
–
3)
This pin gets the horizontal sync information. Either
single or double horizontal frequency or VGA horizon-
tal sync signal.
Pin 64
–
Sync Signal Input
VS
(Fig. 4
–
3)
This pin gets the vertical sync information. Either sin-
gle or double vertical frequency or VGA vertical sync
signal.
Pin 65, 66
–
Crystal Output / Input
XTAL2 / XTAL1
(Fig. 4
–
19)
These pins are connected to an 5-MHz crystal oscilla-
tor. The security unit for the HOUT signal uses this
clock signal as reference.
Pin 67
–
I
2
C Data Input/Output
SDA
(Fig. 4
–
20)
Via this pin the I
2
C-bus data are written to or read from
the DDP 3310B.
Pin 68
–
I
2
C Clock Input
SCL
(Fig. 4
–
20)
Via this pin, the clock signal for the I
2
C-bus will be sup-
plied. The signal can be pulled down by an internal
transistor.
* Application Note
:
All ground pins should be connected separately with
short and low-resistive lines to a central power supply
ground. Accordingly, all supply pins should be con-
nected separately with short and low-resistive lines to
the power supply. Decoupling capacitors from VSUPP
to GNDP, VSUPD to GNDD, and VSUPO to GNDO are
recommended to be placed as closely as possible to
the pins.
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