參數(shù)資料
型號: DD28F032SA-080
廠商: INTEL CORP
元件分類: DRAM
英文描述: 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile⑩ MEMORY
中文描述: 4M X 8 FLASH 12V PROM, 80 ns, PDSO56
封裝: 14 X 20 MM, 1.20 MM HEIGHT, TSOP-56
文件頁數(shù): 32/49頁
文件大?。?/td> 1402K
代理商: DD28F032SA-080
DD28F032SA
E
32
6.7 Power-Up and Reset Timings
RP#
(P)
3/5#
(Y)
0V
3.3V
V Power-Up
5.0V
V
CC
(3V,5V)
4.5V
PLYL
t
t
PL5V
YLPH
t
YHPH
t
Valid 5.0V Outputs
Valid
Valid
Address
(A)
Data
(Q)
Valid 3.3V Outputs
AVQV
t
AVQV
t
PHQV
t
PHQV
t
PHEL3
t
CE #
PHEL5
t
X
0490-13
Figure 13. V
CC
Power-Up and RP# Reset Waveforms
Symbol
Parameter
Notes
Min
Max
Units
t
PLYL
t
PLYH
t
YLPH
t
YHPH
t
PL5V
t
PL3V
t
PHEL3
RP# Low to 3/5# Low (High)
0
μs
3/5# Low (High) to RP# High
1
2
μs
RP# Low to V
CC
at 4.5V Minimum (to V
CC
at
3.0V min or 3.6V max)
2
0
μs
RP# High to CE# Low (3.3V V
CC
)
1
500
t
PHEL5
RP# High to CE# Low (5V V
CC
)
1
330
t
AVQV
Address Valid to Data Valid for V
CC
= 5.0V ± 10%
3
80
ns
t
PHQV
RP# High to Data Valid for V
CC
= 5.0V ± 10%
3
480
ns
NOTES:
CE
0
#, CE
X
# and OE# are switched low after Power-Up.
1. The t
YLPH
/t
YHPH
and t
PHEL3
/t
PHEL5
times must be strictly followed to guarantee all other read and program specifications.
2. The power supply may start to switch concurrently with RP# going low.
3. The address access time and RP# high to data valid time are shown for the DD28F032SA-80 and 5.0V V
CC
operation.
Refer to the AC Characteristics-Read Only Operations for 3.3V V
CC
operation and all other speed options.
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