參數(shù)資料
型號: DD28F032SA-080
廠商: INTEL CORP
元件分類: DRAM
英文描述: 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile⑩ MEMORY
中文描述: 4M X 8 FLASH 12V PROM, 80 ns, PDSO56
封裝: 14 X 20 MM, 1.20 MM HEIGHT, TSOP-56
文件頁數(shù): 30/49頁
文件大?。?/td> 1402K
代理商: DD28F032SA-080
DD28F032SA
E
30
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figures 6 and 7.
2. OE# may be delayed up to t
ELQV
-t
GLQV
after the falling edge of CE
X
# without impact in t
ELQV
.
3. Sampled, not 100% tested.
4. This timing parameter is used to latch the correct BSR data onto the outputs.
5. Device speeds are defined as:
70/80 ns at V
CC
= 5.0V equivalent to
150 ns at V
CC
= 3.3V
100 ns at V
CC
= 5.0V equivalent to
150 ns at V
CC
= V
CC
= 3.3V
6. See AC Input/Output Reverence Waveforms and AC Testing Load Circuits for High Speed Test Configuration.
7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
HIGH Z
HIGH Z
ADDRESSES STABLE
VALID OUTPUT
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
CC
GND
5.0V
V
IH
V
IL
t
t
t
t
t
PHQV
AVQV
GLQV
ELQV
t
GLQX
t
ELQX
t
AVAV
t
EHQZ
t
GHQZ
OH
ADDRESSES (A)
OE# (G)
WE# (W)
DATA (D/Q)
RP# (P)
V
OL
t
AVGL
t
AVEL
CEx# (E)
(1)
V
IL
V
OH
0490-11
NOTES:
For 28F016SA No. 1: CE
X
# is defined as the latter of CE
0
# or CE
1
# going low, or the first of CE
0
# or CE
1
# going high.
For 28F016SA No. 2: CE
X
# is defined as the latter of CE
0
# or CE
2
# going low, or the first of CE
0
# or CE
2
# going high.
Figure 11. Read Timing Waveforms
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