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參數(shù)資料
| 型號(hào)： | CYNSE70032 |
| 英文描述： | Network Processing |
| 中文描述： | 網(wǎng)絡(luò)處理 |
| 文件頁(yè)數(shù)： | 16/126頁(yè) |
| 文件大小： | 3302K |
| 代理商： | CYNSE70032 |
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 16 of 126
9.1
Table 9-2
shows the Read burst address register (RBURREG) fields that must be programmed before a burst Read.
Read Burst Address Register
9.2
Table 9-3
describes the Write burst address register (WBURREG) fields that must be programmed before a burst Write.
Write Burst Address Register Description
9.3
Bit[0] of each 68-bit data entry is specially designated for use in the operation of the Learn command. For 68-bit-configured
quadrants, this bit indicates whether a location is full (bit set to 1) or empty (bit set to 0). Every Write or Learn command loads
the address of the first 68-bit location containing a 0 into the entry’s bit[0]. This is stored in the NFA register (see
Table 9-4
). If all
the bits[0] in a device are set to 1, the CYNSE70032 asserts FULO[1:0] to 1.
For a 136-bit-configured quadrants, the LSB of the NFA register is always set to 0. The host ASIC must set both bit[0] and bit[68]
in a 136-bit word to either 0 or 1 to indicate full or empty status. Both bit[0] and bit[68] must be set to either 0 or 1, (that is, the 10
or 01 settings are invalid).
NFA Register
Table 9-2. Read Burst Register Description
Field
Range
Initial Value
ADR
[13:0]
Description
0
Address
. This is the starting address of the data or mask array during a burst Read
operation. It automatically increments by one for each successive Read of the data or
mask array. Once the operation is complete, the contents of this field must be reinitialized
for the next operation.
Reserved
.
Length of Burst Access
. The device provides the capability to Read from 4–511 locations
in a single burst. The BLEN decrements automatically. Once the operation is complete,
the contents of this field must be reinitialized for the next operation.
Reserved
.
[18:14]
[27:19]
BLEN
0
[67:28]
Table 9-3. Write Burst Register Description
Field
Range
ADR
[13:0]
Initial Value
0
Description
Address
. This is the starting address of the data or mask array during a burst
Write operation. It automatically increments by one for each successive write of
the data or mask array. Once the operation is complete, the contents of this field
must be reinitialized for the next operation.
Reserved
.
Length of Burst Access
. The device provides the capability to write from 4–511
locations in a single burst. The BLEN decrements automatically. Once the
operation is complete, the contents of this field must be reinitialized for the next
operation.
Reserved
.
[18:14]
[27:19]
BLEN
0
[67:28]
Table 9-4. NFA Register
Address
60
67–14
Reserved
13–0
Index
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYNSE70128 | Network Processing |
| CYNSE70256 | Network Processing |
| CZET101 | Clock Driver |
| CZEU101 | Quad Peripheral Driver |
| CZEZ101 | Triple Peripheral Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYNSE70032-66BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Network Search Engine |
| CYNSE70032-66BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Network Search Engine |
| CYNSE70032-83BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Network Search Engine |
| CYNSE70064-50BGC | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70064-83BGC | 制造商:Cypress Semiconductor 功能描述: |
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