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參數(shù)資料
| 型號(hào)： | CY2DP3120 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 92K |
| 代理商： | CY2DP3120 |
PRELIMINARY
FastEdge Series
CY2DP3120
Document #: 38-07514 Rev. *A
Page 9 of 11
-2 V
Z o = 5 0 o h m
-2 V
5 "
5 "
C Y 2 D P 3 1 2 0
R
T
= 5 0 o h m
R
T
= 5 0 o h m
V C C = 0 .0 V
V E E = -3 .3 V
Figure 9. Standard ECL Output Termination
V T T
Z o = 5 0 o h m
5 "
V T T
R
T
= 5 0 o h m
5 "
C Y 2 D P 3 1 2 0
R
T
= 5 0 o h m
V C C
V E E
V B B
Figure 10. Driving a PECL/ECL Single-Ended Input
3 .3 V
Z o = 5 0 o h m
3 .3 V
5 "
5 "
C Y 2 D P 3 1 2 0
1 2 0 o h m
1 2 0 o h m
V C C = 3 .3 V
V E E = 0 V
L V D S
5 1 o h m
(2 p la ce s)
3 3 o h m
(2 p la ce s)
L V P E C L to
L V D S
Figure 11. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) to a Lo
w-Voltage Differential
Signaling (LVDS) Interface
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