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參數(shù)資料
| 型號： | CY2DP3120 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大小： | 92K |
| 代理商： | CY2DP3120 |
PRELIMINARY
FastEdge Series
CY2DP3120
Document #: 38-07514 Rev. *A
Page 6 of 11
Test Configurations
Standard test load using a differential pulse generator and
differential measurement instrument.
Timing Definitions
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
VTT
R
T
= 50 ohm
Zo = 50 ohm
VTT
5"
5"
VTT
R
T
= 50 ohm
DUT
CY2DP3120
R
T
= 50 ohm
R
T
= 50 ohm
Figure 1. CY2DP3120 AC Test Reference
VIH
VIL
VCMR
VPP
VCMR Min = 1.2V
VPP range
0.1V - 1.3V
VCMR Max = VCC
VCC = 3.3V
VCC
VEE
VEE = 0.0V
Figure 2. PECL Waveform Definitions
V
IH
V
IL
V
C M R
VP P
V C C
V EE
V C C = 0.0V
V C M R m ax = 0
V C M R m in V EE - 1.2V
V EE = -2.5V or -3.3V
VP P range = 0.1
to 1.3V
Figure 3. PECL Waveform Definitions
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| CY2DP3120AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:20 Differential Clock/Data Fanout Buffer |
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| CY2DP3120AXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:20 Differential Clock/Data Fanout Buffer |
| CY2DP3120AXIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:20 Differential Clock/Data Fanout Buffer |
| CY2DP314 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1:4 Differential Clock/Data Fanout Buffer |
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