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參數(shù)資料
| 型號： | CY2DP3120 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 92K |
| 代理商： | CY2DP3120 |
PRELIMINARY
FastEdge Series
CY2DP3120
Document #: 38-07514 Rev. *A
Page 5 of 11
Notes:
16. AC characteristics apply for parallel output termination of 50
to VTT.
17. VPP (AC) is the minimum differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew.
18. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and
the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew.
19. The CY2DP3120 is fully operation up to 1.5 GHz.
20. VX(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input
swing lies within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew.
21. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
AC Electrical Specifications
Parameter
Clock Input Pair CLKA, CLKA (PECL or ECL Differential Signals)
V
PP
V
CMR
F
CLK
T
PD
Propagation Delay CLKA or CLKB to
Q0–Q9 Pair
Description
Condition
Min.
Max.
Unit
Differential Input Voltage
[17]
Differential Cross Point Voltage
[18]
Input Frequency
[19]
Differential Operation
Differential Operation
50% Duty Cycle Standard Load
660 MHz 50% Duty Cycle
Standard Load Differential
Operation
0.1
1.3
0
1,500
750
V
V
V
EE
+1.2
MHz
ps
400
Clock Input Pair CLKB, CLKB (HSTL Differential Signals)
V
PP
V
CMR
F
CLK
T
PD
Propagation Delay CLKA or CLKB to
Q0–Q9 Pair
Differential Input Voltage
[17]
Differential Cross Point Voltage
[18]
Input Frequency
[19]
Differential Operation
Differential Operation
50% Duty Cycle Standard Load
660 MHz 50% Duty Cycle
Standard Load Differential
Operation
0.1
1.3
0
1,500
750
V
V
V
EE
+1.2
MHz
ps
400
ECL/PECL Clock Outputs (Q0–19, Q#0–19) (Differential)
Vo
(P-P)
Differential Output Voltage
(Peak-to-Peak)
Differential PRBS
fo < 50 MHz
fo < 0.8 GHz
fo < 1.0 GHz
660-MHz 50% Duty Cycle
Standard Load Differential
Operation
660-MHz 50% Duty Cycle
Standard Load Differential
Operation
660-MHz 50% Duty Cycle
Standard Load Differential
Operation
660-MHz 50% Duty Cycle
Standard Load Differential
Operation
660-MHz 50% Duty Cycle
Differential 20% to 80%
660-MHz 50% Duty Cycle
Standard Load
0.45
0.4
0.375
V
tsk
(O)
Output-to-Output skew
50
ps
tsk
(PP)
Output-to-output skew (part-to-part)
500
ps
T
jitt(cc)
Output cycle-to-cycle jitter (Intrinsic)
10
ps
r.m.s
tsk(P)
Output pulse skew
[21]
ps
T
F
, T
F
Output Rise/Fall time
0.3
ns
TTB
Total Timing Budget
ps
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