參數(shù)資料
型號: CXK79M72C165GB
英文描述: MEMORY-SigmaRAM 16Meg 1x1z LVCMOS I/O (256K x 72) (27 pages 364K Rev. 7/6/01)
中文描述: 內存SigmaRAM 16Meg 1x1z的LVCMOS的I / O(256 × 72)(27頁364K牧師7/6/01)
文件頁數(shù): 18/30頁
文件大?。?/td> 554K
代理商: CXK79M72C165GB
SONY
Σ
RAM CXK79M72C160GB / CXK79M36C160GB / CXK79M18C160GB
Preliminary
18Mb 1x1Lp, HSTL, rev 1.0
18 / 30
July 19, 2002
Two Bank Read-Write-Read Timing Diagram
Note
:
In the diagram above, two Deselect operations are inserted between Read and Write operations to control the data bus transition
from output to input. This depiction is for clarity purposes only. It is NOT a requirement. Depending on the application, one Deselect op-
eration may be sufficient.
Note
: Bank 1 EP1 = “l(fā)ow”, Bank 2 EP1 “high”, and Bank 1 and Bank 2 E2 = EP2 in this example (not shown).
A2
A3
A4
A5
A
E1
DQ (B1)
Q11
D41
Q12
A1
B-Deselect
R-Continue
B-Deselect
Read
B-Deselect
Deselect
Write
B-Deselect
W-Continue B-Deselect
Read
Deselect
B-Deselect
Deselect
Figure 4
CK
CQ (B1)
CQ (B1)
ADV
W
Bx
E2
B1:
B2:
Read
B-Deselect
Deselect
B-Deselect B-Deselect
Write
B-Deselect B-Deselect
DQ (B2)
D32
Q21
D31
Q51
CQ (B2)
CQ (B2)
t
KHCZ
t
KHCX1
CK
相關PDF資料
PDF描述
CXO-M10 Telecommunication IC
CXO-MS10 Telecommunication IC
CXO23HG4I50.0KHZ Peripheral IC
CXO25HG1C41.5MHZ Peripheral IC
CXO25HG1C50.0KHZ Peripheral IC
相關代理商/技術參數(shù)
參數(shù)描述
CXK79M72C165GB-4 制造商:SONY 功能描述:
CXK900L-S 制造商:CHDS 功能描述:HEAT SINK 130x30x10mm
CX-L0612A 制造商:KYOCERA Corporation 功能描述:INVERTER FOR 5.7" DISPLAYS
CXL1008M 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CMOS-CCD Signal Processor for Skew Compensation
CXL1008M/P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CMOS-CCD Signal Processor for Skew Compensation