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CXD3531R
Notes on Handling
The power supply and GND patterns have a large effect on undesired radiation on the substrate and
interference to analog circuits, etc.
General precautions are as follows.
Make the GND pattern as wide as possible. Using a multi-layer substrate and a solid ground is recommended.
Connect each power supply pin to GND via a ceramic chip capacitor of 0.1μF or more located as close to
each pin as possible.
Do not use this IC under conditions other than the recommended operating conditions.
Absolute maximum rating values should not be exceeded even momentarily. Exceeding that ratings may
damage the device, leading to eventual breakdown.
This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be
taken to prevent electrostatic discharge.
Since this IC utilizes a MOS structure, it may latch up due to excessive noise or power surge greater than the
maximum rating of the I/O pins, interface with two power supplies of another circuit, or the order in which
power is supplied to circuits. Make a thorough study of measures against the possibility of latch up before
use.
When the initialization of this IC is performed at power-on, system clear cancellation is performed after the
supply voltage is set in the range of the recommended operating conditions and stabilized. Keep in mind that
the internal circuit may not be initialized correctly if system clear cancellation is performed before the supply
voltage is set in the range of the recommended operating conditions.
When designing the substrate, take sufficient care for the surrounding temperature and heat radiation, and
make sure the IC junction temperature does not exceed the maximum value.
Be sure to make the number of dot clocks input to the CXD3531R in 1H an even number. Note that if there is
an odd number of dot clocks, the internal phase compensation PLL will not operate properly.
Be sure to make a thorough evaluation of any items not listed in this data sheet.