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參數資料
| 型號： | CWMPCEVB5200BE |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 63/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD MPC5200B W/256MB |
| 標準包裝： | 1 |
| 類型： | MPU |
| 適用于相關產品： | MPC5200B |
| 所含物品： | 板 |
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MPC5200B Data Sheet, Rev. 4
66
Freescale Semiconductor
3.3.2
Pull-up Requirements for the PCI Control Lines
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local
Bus specification. This is also required for MOST/Graphics and Large Flash Mode.
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain
stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL,
PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.
3.3.3
Pull-up/Pull-down Requirements for MEM_MDQS Pins (SDRAM)
The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down resistors in SDRAM mode.
3.3.4
.
Pull-up/Pull-down Requirements for MEM_MDQS Pins (DDR 16-bit
Mode)
The MEM_MDQS[1:0] signals are not used in DDR 16-bit mode and require pull-down resistors.
3.4
JTAG
The MPC5200B provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common
On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the
MPC5200B's embedded Freescale (formerly Motorola) MPC603e e300 processor. This interface provides a means for
executing test routines and for performing software development and debug functions.
3.4.1
JTAG_TRST
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1
specification but is provided on all processors that implement the PowerPC architecture. To obtain a reliable power-on reset
performance, the JTAG_TRST signal must be asserted during power-on reset.
3.4.1.1
JTAG_TRST and PORRESET
The JTAG interface can control the direction of the MPC5200B I/O pads via the boundary scan chain. The JTAG module must
be reset before the MPC5200B comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released.
For more details refer to the Reset and JTAG Timing Specification.
Figure 53. PORRESET vs. JTAG_TRST
3.4.1.2
Connecting JTAG_TRST
The wiring of the JTAG_TRST depends on the existence of a board-related debug interface. (see below)
JTAG_TRST
PORRESET
Required assertion of JTAG_TRST
Optional assertion of JTAG_TRST
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CWMPCEVB5200BE | 制造商:Freescale Semiconductor 功能描述:MPC5200B BOARD W/ 256MB |
| CWMPH1 | 功能描述:電線導管 In-Cabinet Horizontal Cable Manager Fron RoHS:否 制造商:Panduit 類型:Slotted SideWall Open finger design wiring cut 材料:Polypropylene 顏色:Light Gray 大小: 最大光束直徑: 抗拉強度: 外部導管寬度:25 mm 外部導管高度:25 mm |
| CWMPH1Y | 制造商:Panduit Corp 功能描述:PANDUIT |
| CWMPHF1 | 功能描述:電線導管 In-Cabinet Horizontal Cable Manager Fron RoHS:否 制造商:Panduit 類型:Slotted SideWall Open finger design wiring cut 材料:Polypropylene 顏色:Light Gray 大小: 最大光束直徑: 抗拉強度: 外部導管寬度:25 mm 外部導管高度:25 mm |
| CWMPV2318 | 功能描述:電線導管 In-Cabinet Vertical Cable Manager 18 RU RoHS:否 制造商:Panduit 類型:Slotted SideWall Open finger design wiring cut 材料:Polypropylene 顏色:Light Gray 大小: 最大光束直徑: 抗拉強度: 外部導管寬度:25 mm 外部導管高度:25 mm |
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