- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17034 > CWMPCEVB5200BE (Freescale Semiconductor)BOARD MPC5200B W/256MB PDF資料下載
參數(shù)資料
| 型號： | CWMPCEVB5200BE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD MPC5200B W/256MB |
| 標準包裝： | 1 |
| 類型： | MPU |
| 適用于相關(guān)產(chǎn)品： | MPC5200B |
| 所含物品： | 板 |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
MPC5200B Data Sheet, Rev. 4
12
Freescale Semiconductor
1.3
AC Electrical Characteristics
Hyperlinks to the indicated timing specification sections are provided below.
1.3.1
AC Test Timing Conditions:
Unless otherwise noted, all test conditions are as follows:
TA = –40 to 85 oC
Tj = –40 to 115 oC
VDD_CORE = 1.42 to 1.58 V
VDD_IO = 3.0 to 3.6 V
Table 11. e300 PLL Specifications
Characteristic
Sym
Notes
Min
Typical
Max
Unit
SpecID
e300 frequency
fcore
(1)
1 The XLB_CLK frequency and e300 PLL Configuration bits must be chosen such that the resulting system
frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies in Table 12.
50
—
550
MHz
O4.1
e300 cycle time
tcore
2.85
—
40.0
ns
O4.2
e300 VCO frequency
fVCOcore
400
—
1200
MHz
O4.3
e300 input clock frequency
fXLB_CLK
—
25
—
367
MHz
O4.4
e300 input clock cycle time
tXLB_CLK
—
2.73
—
50.0
ns
O4.5
e300 input clock jitter
tjitter
(2)
2 This represents total input jitter—short term and long term combined—and is guaranteed by design. Two different
types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected.
Systemic jitter is passed into and through the PLL to the internal clock circuitry.
—
150
ps
O4.6
e300 PLL relock time
tlock
(3)
3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required
for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
—
100
μsO4.7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 0210490246 | CABLE JUMPER 1.25MM .178M 18POS |
| 0210490245 | CABLE JUMPER 1.25MM .178M 18POS |
| 0210390953 | CABLE JUMPER 1MM .152M 25POS |
| RBC08DRYI-S734 | CONN EDGECARD 16POS DIP .100 SLD |
| LGU2E471MELA | CAP ALUM 470UF 250V 20% SNAP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CWMPCEVB5200BE | 制造商:Freescale Semiconductor 功能描述:MPC5200B BOARD W/ 256MB |
| CWMPH1 | 功能描述:電線導(dǎo)管 In-Cabinet Horizontal Cable Manager Fron RoHS:否 制造商:Panduit 類型:Slotted SideWall Open finger design wiring cut 材料:Polypropylene 顏色:Light Gray 大小: 最大光束直徑: 抗拉強度: 外部導(dǎo)管寬度:25 mm 外部導(dǎo)管高度:25 mm |
| CWMPH1Y | 制造商:Panduit Corp 功能描述:PANDUIT |
| CWMPHF1 | 功能描述:電線導(dǎo)管 In-Cabinet Horizontal Cable Manager Fron RoHS:否 制造商:Panduit 類型:Slotted SideWall Open finger design wiring cut 材料:Polypropylene 顏色:Light Gray 大小: 最大光束直徑: 抗拉強度: 外部導(dǎo)管寬度:25 mm 外部導(dǎo)管高度:25 mm |
| CWMPV2318 | 功能描述:電線導(dǎo)管 In-Cabinet Vertical Cable Manager 18 RU RoHS:否 制造商:Panduit 類型:Slotted SideWall Open finger design wiring cut 材料:Polypropylene 顏色:Light Gray 大小: 最大光束直徑: 抗拉強度: 外部導(dǎo)管寬度:25 mm 外部導(dǎo)管高度:25 mm |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。