參數(shù)資料
型號: CWMPCEVB5200BE
廠商: Freescale Semiconductor
文件頁數(shù): 46/72頁
文件大?。?/td> 0K
描述: BOARD MPC5200B W/256MB
標準包裝: 1
類型: MPU
適用于相關產品: MPC5200B
所含物品:
MPC5200B Data Sheet, Rev. 4
50
Freescale Semiconductor
Figure 40. Timing Diagram — IrDA Transmit Line
1.3.16.4
SPI Mode
NOTE
Output timing is specified at a nominal 50 pF load.
Table 46. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)
Sym
Description
Min
Max
Units
SpecID
1
SCK cycle time, programable in the PSC CCS register
30.0
ns
A15.26
2
SCK pulse width, 50% SCK duty cycle
15.0
ns
A15.27
3
Slave select clock delay, programable in the PSC CCS register
30.0
ns
A15.28
4
Output Data valid after Slave Select (SS)
8.9
ns
A15.29
5
Output Data valid after SCK
8.9
ns
A15.30
6
Input Data setup time
6.0
ns
A15.31
7
Input Data hold time
1.0
ns
A15.32
8
Slave disable lag time
8.9
ns
A15.33
9
Sequential Transfer delay, programable in the PSC CTUR / CTLR
register
15.0
ns
A15.34
10
Clock falling time
7.9
ns
A15.35
11
Clock rising time
7.9
ns
A15.36
IrDA_TX
4
3
(SIR / FIR / MIR)
12
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