System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on OMCK after reset. Wh" />
參數(shù)資料
型號(hào)： CS8416-CNZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 9/37頁(yè)
文件大?。?/td> 0K
描述： IC RCVR DGTL 192KHZ 28QFN COMM
標(biāo)準(zhǔn)包裝： 490
類(lèi)型： 數(shù)字音頻接口接收器
應(yīng)用： 數(shù)字音頻
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-QFN
供應(yīng)商設(shè)備封裝： 28-QFN 裸露焊盤(pán)（5x5）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 759 (CN2011-ZH PDF)
配用： 598-1017-ND - BOARD EVAL FOR CS8416 RCVR
其它名稱(chēng)： 598-1723
DS578F3
17
CS8416
OMCK
25
System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on
OMCK after reset. When enabled, the clock signal input on this pin is automatically output through
RMCK
24
Input Section Recovered Master Clock (Output) - Input section recovered master clock output
from the PLL. Frequency is 256x the sample rate (Fs) when the U pin is pulled down by a 47 kΩ
resistor to DGND. Frequency is 128x the sample rate (Fs) when the U pin is pulled up by a 47 kΩ
resistor to VL.
OSCLK
27
Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin
OLRCK
28
Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT pin. Frequency will be the output sample rate (Fs)
SDOUT
26
Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled low to
DGND through a 47 k
Ω resistor to place the part in Hardware Mode.
RXSEL1
RXSEL0
10
11
Receiver MUX Selector (Input) - Used to select which pin, RXP[3:0], is used for the receiver input.
TXSEL1
TXSEL0
12
13
TX Pin MUX SELECTION (Input) - Used to select which pin, RXP[3:0], is passed to the TX pin out-
put. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs.
TX
20
S/PDIF MUX Passthrough (Output) - Single-ended signal is resolved to full-rail, but is not de-jittered
before it is output. Output is set by TXSEL[1:0]. This pin is also used to select the type of phase
detector (PDUR) at reset. If TX passthrough is not used, the user should set it to output one of the
unused receiver inputs.
NV/RERR
14
Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is selected
by a 47 k
Ω resistor to DGND. RERR is selected by a 47 kΩ resistor to VL.
AUDIO
15
Audio Channel Status Bit (Output) – When low, a valid linear PCM audio stream is indicated. See
“Non-Audio Detection” on page 31. This pin is also used to select the serial port format (SFSEL1) at
reset.
96KHZ
16
96 kHz Sample Rate Detect (Output) - If the input sample rate is
≤ 48 kHz, outputs a “0”. Outputs a
“1” if the sample rate is
≥ 88.1 kHz. Otherwise the output is indeterminate. Also used to set the
Emphasis Audio Match feature at reset.
RCBL
17
Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block.
RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames and then
returns low for the remainder of the block. RCBL changes on rising edges of RMCK. Also used to set
the serial audio port to master or slave at reset.
C19
Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the
rising and falling edges of OLRCK. Also used to select the serial port format (SFSEL0) at reset.
U18
User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling
edges of OLRCK. Also used to select the frequency of RMCK to either 256*Fs or 128*Fs at reset.
Pin Name
Pin #
Pin Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS8416-CNZ 制造商:Cirrus Logic 功能描述:Receiver IC RoHS Compliant:Yes
CS8416-CNZR 功能描述:音頻發(fā)送器、接收器、收發(fā)器 IC 192 kHz Digital Audio Receiver RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類(lèi)型:I2C, SPI 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝:
CS8416-CS 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
CS8416-CSR 制造商:Cirrus Logic 功能描述:- Tape and Reel
CS8416CSZ 制造商:Cirrus Logic 功能描述:
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