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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� CS8416-CNZ
寤犲晢锛� Cirrus Logic Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 8/37闋�(y猫)
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鎻忚堪锛� IC RCVR DGTL 192KHZ 28QFN COMM
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灏佽/澶栨锛� 28-QFN
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 28-QFN 瑁搁湶鐒婄洡(p谩n)锛�5x5锛�
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 759 (CN2011-ZH PDF)
閰嶇敤锛� 598-1017-ND - BOARD EVAL FOR CS8416 RCVR
鍏跺畠鍚嶇ū(ch膿ng)锛� 598-1723
16
DS578F3
CS8416
3. PIN DESCRIPTION - HARDWARE MODE
3.1
TSSOP Pin Description
Pin Name
Pin #
Pin Description
VA
6
Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little
noise as possible since noise on this pin will directly affect the jitter performance of the recovered
clock
VD
23
Digital Power (Input) 鈥� Digital core power supply. Nominally +3.3 V
VL
21
Logic Power (Input) 鈥� Input/Output power supply. Nominally +3.3 V or +5.0 V
AGND
7
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be
connected to a common ground area under the chip.
DGND
22
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-
nected to a common ground area under the chip.
RST
9
Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are
reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks
are stable in frequency and phase.
FILT
8
PLL Loop Filter (Output) - An RC network should be connected between this pin and analog
ground.
For minimum PLL jitter, return the ground end of the filter network directly to AGND. See 鈥淧LL Filter鈥�
on page 53 for more information on the PLL and the external components.
RXP0
RXP1
RXP2
RXP3
4
3
2
1
Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or
S/PDIF encoded digital data. The RXP[3:0] inputs comprise the 4:2 S/PDIF Input Multiplexer. The
select line control is accessed using the RXPSEL[1:0] pins. Unused multiplexer inputs should be left
for recommended input circuits.
RXN
5
Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or
S/PDIF encoded digital data. Used along with RXP[3:0] to form an AES3 differential input. In single-
ended operation this should be AC coupled to ground through a capacitor. See 鈥淓xternal
RXP3
OLRCK
RXP2
OSCLK
RXP1
SDOUT
RXP0
OMCK
RXN
RMCK
VA
VD
AGND
DGND
FILT
VL
RST
TX
RXSEL1
C
RXSEL0
U
TXSEL1
RCBL
TXSEL0
96KHZ
NV / RERR
AUDIO
1
2
3
4
5
6
7
821
22
23
24
25
26
27
28
9
10
11
12
17
18
19
20
13
14
15
16
Top-Down View
28-pin SOIC/TSSOP
Package
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
CS8416-CNZ 鍒堕€犲晢:Cirrus Logic 鍔熻兘鎻忚堪:Receiver IC RoHS Compliant:Yes
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