參數(shù)資料
型號(hào)： CS8416-CNZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 21/37頁(yè)
文件大?。?/td> 0K
描述： IC RCVR DGTL 192KHZ 28QFN COMM
標(biāo)準(zhǔn)包裝： 490
類(lèi)型： 數(shù)字音頻接口接收器
應(yīng)用： 數(shù)字音頻
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-QFN
供應(yīng)商設(shè)備封裝： 28-QFN 裸露焊盤(pán)（5x5）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 759 (CN2011-ZH PDF)
配用： 598-1017-ND - BOARD EVAL FOR CS8416 RCVR
其它名稱(chēng)： 598-1723
28
DS578F3
CS8416
The second output of the input multiplexer is used to provide the selected input as a source to be output
on a GPO pin. This pass through signal is selected by TXSEL[2:0] in control port register 04h. This single-
ended signal is resolved to full-rail, but is not de-jittered before it is output.
8.1.3
Hardware Mode
In Hardware Mode the input to the decoder is selected by dedicated pins, RXSEL[1:0].
The pass through signal is selected by dedicated pins, TXSEL[1:0] for output on the dedicated TX pin.
This single-ended signal is resolved to full-rail, but is not de-jittered before it is output.
Selectable inputs are restricted to RXP0 to RXP3 for both the receiver and the TX output pin. These inputs
are selected by RXSEL[1:0] and TXSEL[1:0] respectively.
8.2
OMCK System Clock Mode
A special clock switching mode is available that allows the OMCK clock input to automatically replace
RMCK when the PLL becomes unlocked. This is accomplished without spurious transitions or glitches on
RMCK. In Hardware Mode this feature is enabled by a transition (rising edge active) on the OMCK pin after
reset. Therefore to not enable the clock switching feature in Hardware Mode, OMCK should be tied to DGND
or VL. However, in Hardware Mode, once the clock switching feature has been enabled, it can only be dis-
abled by resetting the part. In Software Mode the automatic clock switching feature is enabled by setting
SWCLK bit in Control1 register to a “1”. Additionally in Software Mode, OMCK can be manually forced to
output on RMCK by using the FSWCLK bit in the Control0 register.
When the clock switching feature is enabled, OSCLK and OLRCK are derived from the OMCK input when
the clock has been switched and the serial port is in master mode. When clock switching is enabled and the
PLL is not locked, OLRCK will be OMCK/256 and OSCLK will be OMCK/4. When the PLL loses lock, the
frequency of the VCO drops to ~750 kHz. When this system clock mode is not enabled, the OSCLK and
OLRCK will be based on the VCO when the PLL is not locked and has reached its steady-state idle frequen-
cy. Table 2 shows an example of output clocks based on clock switching being enabled or disabled.
8.3
Clock Recovery and PLL Filter
Please see “PLL Filter” on page 53 for a general description of the PLL, selection of recommended PLL filter
components, and layout considerations. Figures 5 and 6 show the recommended configuration of the two
capacitors and one resistor that comprise the PLL filter.
Clock Switching
Enabled/Disabled
PLL
Locked/Unlocked
RMCK Clock
Ratio
RMCK
OSCLK
OLRCK
Disabled
Locked
128*Fs
6.144 MHz
3.072 MHz
48 kHz
Enabled
Locked
128*Fs
6.144 MHz
3.072 MHz
48 kHz
Disabled
Unlocked
128*Fs
~375 kHz
~187.5 kHz
~2.925 kHz
Enabled
Unlocked
128*Fs
11.2896 MHz
2.8224 MHz
44.1 kHz
Disabled
Locked
256*Fs
12.288 MHz
3.072 MHz
48 kHz
Enabled
Locked
256*Fs
12.288 MHz
3.072 MHz
48 kHz
Disabled
Unlocked
256*Fs
~750 kHz
~187.5 kHz
~2.925 kHz
Enabled
Unlocked
256*Fs
11.2896 MHz
2.8224 MHz
44.1 kHz
Example with OMCK = 11.2896 MHz, the receiver input sample rate = 48 kHz,
OSLCK = 64*Fs, and FSWCLK (Software Mode only) = ‘0’.
Table 2. Clock Switching Output Clock Rates
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS8416-CNZ 制造商:Cirrus Logic 功能描述:Receiver IC RoHS Compliant:Yes
CS8416-CNZR 功能描述:音頻發(fā)送器、接收器、收發(fā)器 IC 192 kHz Digital Audio Receiver RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類(lèi)型:I2C, SPI 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝:
CS8416-CS 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:192 kHZ DIGITAL AUDIO INTERFACE RECEIVER
CS8416-CSR 制造商:Cirrus Logic 功能描述:- Tape and Reel
CS8416CSZ 制造商:Cirrus Logic 功能描述:
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