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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | CS8416-CNZ |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 3/37闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC RCVR DGTL 192KHZ 28QFN COMM |
| 妯欐簴鍖呰锛� | 490 |
| 椤炲瀷锛� | 鏁�(sh霉)瀛楅煶闋绘帴鍙ｆ帴鏀跺櫒 |
| 鎳夌敤锛� | 鏁�(sh霉)瀛楅煶闋� |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 28-QFN |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 28-QFN 瑁搁湶鐒婄洡锛�5x5锛� |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 759 (CN2011-ZH PDF) |
| 閰嶇敤锛� | 598-1017-ND - BOARD EVAL FOR CS8416 RCVR |
| 鍏跺畠鍚嶇ū锛� | 598-1723 |
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DS578F3
11
CS8416
SWITCHING CHARACTERISTICS - CONTROL PORT- IC FORMAT
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Notes:
15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-100
kHz
Bus Free Time Between Transmissions
tbuf
4.7
-
s
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
s
Clock Low time
tlow
4.7
-
s
Clock High Time
thigh
4.0
-
s
Setup Time for Repeated Start Condition
tsust
4.7
-
s
SDA Hold Time from SCL Falling
thdd
10
-
ns
SDA Setup time to SCL Rising
tsud
250
-
ns
Rise Time of SCL and SDA
tr
-
1000
ns
Fall Time SCL and SDA
tf
-300
ns
Setup Time for Stop Condition
tsusp
4.7
-
s
t buf
t hdst
t
low
t r
t f
t
hdd
t high
t sud
t sust
t susp
Stop
Start
Stop
Repeated
SDA
SCL
Figure 4. IC Mode Timing
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|---|---|
| CS8416-CNZ | 鍒堕€犲晢:Cirrus Logic 鍔熻兘鎻忚堪:Receiver IC RoHS Compliant:Yes |
| CS8416-CNZR | 鍔熻兘鎻忚堪:闊抽牷鐧�(f膩)閫佸櫒銆佹帴鏀跺櫒銆佹敹鐧�(f膩)鍣� IC 192 kHz Digital Audio Receiver RoHS:鍚� 鍒堕€犲晢:Cirrus Logic 宸ヤ綔闆绘簮闆诲:3.3 V, 5 V 闆绘簮闆绘祦:11.8 mA 閫氶亾鏁�(sh霉)閲�:1 鏈€澶у伐浣滄韩搴�:+ 70 C 鎺ュ彛椤炲瀷:I2C, SPI 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:TSSOP-28 灏佽: |
| CS8416-CS | 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:192 kHZ DIGITAL AUDIO INTERFACE RECEIVER |
| CS8416-CSR | 鍒堕€犲晢:Cirrus Logic 鍔熻兘鎻忚堪:- Tape and Reel |
| CS8416CSZ | 鍒堕€犲晢:Cirrus Logic 鍔熻兘鎻忚堪: |
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