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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | CS53L21-CNZR |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 23/26闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC ADC STEREO 24BIT 98DB 32-QFN |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 6,000 |
| 浣嶆暩(sh霉)锛� | 24 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 100k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 2 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 30mW |
| 闆诲闆绘簮锛� | 妯℃摤鍜屾暩(sh霉)瀛� |
| 宸ヤ綔婧害锛� | -10°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 32-QFN |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 32-QFN锛�5x5锛� |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 3 鍊�(g猫)鍠锛屽柈妤� |
| 閰嶇敤锛� | 598-1550-ND - BOARD EVAL FOR CS53L21 ADC |
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6
DS700PP1
CS53L21
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
Pin Name
#
Pin Description
LRCK
1
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SDA/CDIN
(MCLKDIV2)
2
Serial Control Data (Input/Output) - SDA is a data I/O in IC Mode. CDIN is the input data line for the
control port interface in SPI Mode.
MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.
SCL/CCLK
(IS/LJ)
3
Serial Control Port Clock (Input) - Serial clock for the serial control port.
Interface Format Selection (Input) - Hardware Mode: Selects between IS & Left-Justified interface for-
mats for the ADC.
AD0/CS
(TSTN)
4
Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode; CS
is the chip-select signal for SPI format.
Test In (Input) - Hardware Mode: This pin is an input used for test purposes only and should be tied to
DGND for normal operation.
VA_PULLUP
5
Reference Pull-up (Input) - This pin is an input used for test purposes only and must be pulled-up to VA
using a 47 k
惟 resistor.
TSTO
6
Test Out (Output) - This pin is an output used for test purposes only and must be left 鈥渇loating鈥� (no con-
nection external to the pin).
AGND
7
Analog Ground (Input) - Ground reference for the internal analog section.
TSTO
8
Test Out (Output) - This pin is an output used for test purposes only and must be left 鈥渇loating鈥� (no con-
nection external to the pin).
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CS53L21
VD
DGND
SDOUT
(M/S
)
MCLK
TSTN
SCLK
TSTO
NIC
VA
AGND
TST
O
FILT
+
VQ
SDA/CDIN (MCLKDIV2)
SCL/CCLK (IS/LJ)
AD0/CS (TSTN)
TSTO
VL
RESET
AGND
TSTO
AFILTA
AIN1A
AIN1B
AIN2A
AIN2B/BIAS
MICIN1/AIN3A
MICIN2/BIAS/AIN3B
AFILTB
VA_PULLUP
LRCK
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