參數(shù)資料
型號(hào): CS53L21-CNZR
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 1/26頁(yè)
文件大?。?/td> 0K
描述: IC ADC STEREO 24BIT 98DB 32-QFN
標(biāo)準(zhǔn)包裝: 6,000
位數(shù): 24
采樣率(每秒): 100k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 30mW
電壓電源: 模擬和數(shù)字
工作溫度: -10°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-QFN
供應(yīng)商設(shè)備封裝: 32-QFN(5x5)
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 3 個(gè)單端,單極
配用: 598-1550-ND - BOARD EVAL FOR CS53L21 ADC
Copyright
Cirrus Logic, Inc. 2006
(All Rights Reserved)
Preliminary Product Information This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
MAY ‘06
DS700PP1
Low Power, Stereo Analog to Digital Converter
FEATURES
98 dB Dynamic Range (A-wtd)
-88 dB THD+N
Analog Gain Controls
– +32 dB or +16 dB MIC Pre-Amplifiers
– Analog Programmable Gain Amplifier
(PGA)
+20 dB Digital Boost
Programmable Automatic Level Control (ALC)
– Noise Gate for Noise Suppression
– Programmable Threshold and
Attack/Release Rates
Independent Left/Right Channel Control
Digital Volume Control
High-Pass Filter Disable for DC Measurements
Stereo 3:1 Analog Input MUX
Dual MIC Inputs
– Programmable, Low Noise MIC Bias Levels
– Differential MIC Mix for Common Mode
Noise Rejection
Very Low 64 Fs Oversampling Clock Reduces
Power Consumption
SYSTEM FEATURES
24-bit Conversion
4 kHz to 96 kHz Sample Rate
Multi-bit Delta Sigma Architecture
Low Power Operation
– Stereo Record (ADC): 8.72 mW @ 1.8 V
– Stereo Record (MIC to PGA and ADC):
13.73 mW @ 1.8 V
Variable Power Supplies
– 1.8 V to 2.5 V Digital & Analog
– 1.8 V to 3.3 V Interface Logic
Power Down Management
– ADC, MIC Pre-Amplifier, PGA
Software Mode (IC & SPI
Control)
Hardware Mode (Stand-Alone Control)
Flexible Clocking Options
– Master or Slave Operation
Digital Routing Mixes
– Mono Mixes
1.8 V to 3.3 V
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Serial Audio
Output
1.8 V to 2.5 V
MUX
PGA
PCM
Seri
al
In
te
rf
a
ce
Register
Configuration
Le
ve
lTranslato
r
Reset
Software Mode
Stereo Input 1
Stereo Input 2
Stereo Input 3 /
Mic Input 1 & 2
PGA
+32 dB
Volume
Controls
ALC
MIC
Bias
MUX
High Pass
Filters
ALC
Digital
Signal
Processing
Engine
Hardware Mode
or I2C & SPI
Control Data
CS53L21
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