參數(shù)資料
型號： CS4351-DZZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 7/37頁
文件大?。?/td> 0K
描述： IC DAC STER 112DB 192KHZ 20TSSOP
標準包裝： 74
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 354mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 20-TSSOP
包裝： 托盤
輸出數(shù)目和類型： 2 電壓，單極
采樣率（每秒）： 192k
配用： 598-1152-ND - BOARD EVAL FOR CS4351 DAC
DS566F1
15
CS4351
4. APPLICATIONS
4.1
Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode will
depend on whether the Auto-Detect Defeat bit is enabled/disabled.
4.1.1
Auto-Detect Enabled
The Auto-Detect feature is enabled by default. In this state, the CS4351 will auto-detect the correct mode
when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated
in Table 1. Sample rates outside the specified range for each mode are not supported.
4.1.2
Auto-Detect Disabled
The Auto-Detect feature can be defeated only by the format bits in the control port register 02h. In this
state, the CS4351 will not auto-detect the correct mode based on the input sample rate (Fs). The opera-
tional mode must then be set manually according to one of the ranges illustrated in Table 2. Please refer
to Section 6.2.3 for implementation details. Sample rates outside the specified range for each mode are
not supported. In stand-alone mode it is not possible to disable auto-detect of sample rates.
4.2
System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.
The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the
MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard au-
dio sample rates and the required MCLK frequency, are illustrated in Tables 3 through 5.
Refer to Section 4.3 for the required SCLK timing associated with the selected Digital Interface Format and
frequencies.
Input Sample Rate (FS)MODE
4 kHz - 50 kHz
Single-Speed Mode
84 kHz - 100 kHz
Double-Speed Mode
170 kHz - 200 kHz
Quad-Speed Mode
Table 1. CS4351 Auto-Detect
FM1
FM0
Input Sample Rate (FS)MODE
0
Auto speed mode detect
Auto
0
1
4 kHz - 50 kHz
Single-Speed Mode
1
0
50 kHz - 100 kHz
Double-Speed Mode
1
100 kHz - 200 kHz
Quad-Speed Mode
Table 2. CS4351 Mode Select
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