參數(shù)資料
型號(hào)： CS4351-DZZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 11/37頁(yè)
文件大?。?/td> 0K
描述： IC DAC STER 112DB 192KHZ 20TSSOP
標(biāo)準(zhǔn)包裝： 74
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 354mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 托盤
輸出數(shù)目和類型： 2 電壓，單極
采樣率（每秒）： 192k
配用： 598-1152-ND - BOARD EVAL FOR CS4351 DAC
DS566F1
19
CS4351
4.6.2
Power-Down
To prevent audible transients at power-down, the device must first enter its power-down state. When this
occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB.
In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly dis-
charge. Once this charge is dissipated, the power to the device may be turned off and the system is ready
for the next power-on.
4.6.3
Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-
fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will
occur when the audio outputs are initially clamped to GND. The time that the device must remain in the
power-down state is related to the value of the DC-blocking capacitance and the output load. For example,
with a 3.3 F capacitor, the minimum power-down time will be approximately 0.4 seconds.
4.7
Mute Control
The Mute Control pins go active during power-up initialization, reset, muting (see Section 6.4.3), or if the
MCLK to LRCK ratio is incorrect. These pins are intended to be used as control for external mute circuits to
prevent the clicks and pops that can occur in any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min-
imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Please see the “Typical Connection Diagram” on page 14 for a suggested mute circuit for single supply sys-
tems. This FET circuit must be placed in series after the RC filter, otherwise noise may occur during muting
conditions. Further ESD protection will need to be taken into consideration for the FET used. If dual supplies
are available, the BJT mute circuit from Figure 12 in the CS4398 datasheet (active Low) may be used.
4.8
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4351 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 4 shows the recommended power ar-
rangements, with VA_H, VA, VD, and VL connected to clean supplies. If the ground planes are split between
digital ground and analog ground, the GND pins of the CS4351 should be connected to the analog ground
plane.
All signals, especially clocks, should be kept away from the VBIAS and VQ pins in order to avoid unwanted
coupling into the DAC.
4.8.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling ca-
pacitor should still be placed on each supply pin.
Note:
All decoupling capacitors should be referenced to analog ground.
The CDB4351 evaluation board demonstrates the optimum layout and power supply arrangements.
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